clock buffer chain jitter measurement under deterministic supply noise

Hi all,

I am using pss+pnoise to measure Jee of intermediate nodes and final output in a clock buffer chain, whose power supply is 0.75V. And there is a 100MHz 1mV-amplitude sinusoidal on top of the power supply DC.

The operating frequency of the buffer chain is 8GHz.

1) Is it correct to set beat frequency as 100M? As shown in 1st picture.

2) Since the beat frequency is 1/80 of the clock frequency, is it correct to set "sample ratio" in pnoise to capture the correct clock edge in the measurement? As shown in 2nd picture.

3) In this test bench, I would like to measure the Jee due to both thermal noise of the circuit and power supply. Could you point me to some material? I usually see material about PSS+PXF to measure transfer function from power supply to output.

Thanks and regards,

Yutao