Hi, all
I'm going to test the gate leakage current in TSMC 180nm process.
I connect a DC voltage to the gate of an NMOS transistor, and do DC(and tran) simulation, the results of Ig is nan. I'd like to ask if I'm running the right simulation? Does tsmc 180nm support to test the gate leakage current? Do I need to set some parameters in cadence?
I'm looking forward to your reply|!!!
Best