After reading most of the documentation about how to setup PSS for ring-oscillators, etc. I was able to simulate the ring-VCO with an subsequent div-by-2 in PSS with PNOISE and got reasonable results.
All the blocks are analog (spice/spectre), only the control signals are generated from Verilog-A blocks. I do see some warnings about the Verilo-A blocks.
- fvco=480M, fdiv2=240MHz --> beat-freq=240MHz, conservative, 600 harmonics, tstab=500n
- autonomous circuit: osc-node+ is the ringo-vco output net
- cmin=4fF ( to have not ideal sharp edges)
The next step towards a full PLL feedback loop simulation was to add another div-by-12 frequency divider in series to the div-by-2 --> did not achieve convergence yet, but tested the following settings
- beat-freq=20MHz, tstab=500n, maxstep=1ps (or none)
- osc-node+ is either ringvco-output(480MHz) or fbdiv12-output(20MHz), but none did converge the PSS simulation
- trap vs. gear2only
The Conv norm value is sometimes below 1, but still does not converge.
1. Any idea what I can do to achieve convergence ?
2. A collerague told me (from his experience) to set the beat-freq to 20MHz/3=6.6667MHz, but he could not tell me why this would be advantageous - do you have any idea )
The final goal is to simulate the complete PLL, which will then be a driven circuit with a reference signal (no osc-node+ required).
But first I want to achieve convergence for "ring-vco+divby2+divby12".
Attached is the spectre.out (at least I drag and dropped it into the editor, but cannot see it) ... ?