I'm using IC617, AMS simulator. My netlist includes verilog, verilogams, veriloga, spectre..and real implementation
in my testbench, Block "stimulus" is verilog, and there is a "dumpfile()" in it. Is there a way to transform all signals to ditial signals, and save them in fsdb format?
for analog signal, just transform them to high/low, I know this is possible in VCS+XA simulaiton, is it possible in Cadence AMS?