Accessing simulation variables in verilog-a without passed parameter?

In Verilog-AMS, I am able to access simulation variables in a module by using:

cds_globals.<name of variable>

I'm trying to keep my design as clean as possible, and I don't want to add a parameter to the veriloga view (the other views do not need a passed parameter).  Is there a way to access simulation variables without passing them as a parameter?  I don't want to use the AMS simulator.

Thanks.