Hi everyone,
I am using a different version of cadence for Verilog simulation. I am facing the error message of "eval: unbound variable - _simOneStepXmvlog" while saving my code. Any thoughts on how to fix this error?
Hi everyone,
I am using a different version of cadence for Verilog simulation. I am facing the error message of "eval: unbound variable - _simOneStepXmvlog" while saving my code. Any thoughts on how to fix this error?