Hi everyone,
I am using a different version of cadence for Verilog simulation. I am facing the error message of "eval: unbound variable - _simOneStepXmvlog" while saving my code. Any thoughts on how to fix this error?
↧
Channel:
Cadence Custom IC Design Forum
X
Are you the publisher?
Claim or
contact us
about this channel.
X
0
Channel Details:
- Title: Cadence Custom IC Design Forum
- Channel Number: 3711455
- Language: English
- Registered On: July 11, 2012, 10:00 pm
- Number of Articles: 4953
- Latest Snapshot: July 15, 2025, 2:13 pm
- RSS URL: http://feeds.feedburner.com/cadence/community/forums/38
- Publisher: https://community.cadence.com/cadence_technology_forums/f/custom-ic-design
- Description:
- Catalog: //kittereen4.rssing.com/catalog.php?indx=3711455
© 2025 //www.rssing.com