2-stage CMOS OTA: LVS errors

Hello all,

I've been trying to build a layout for a 2-stage CMOS circuit. I've already checked and corrected with DRC (even though I still get "hot nwell" info on the transistors that are connected to VDD, despite me creating a contact with ND to MET1 and placing an ntub on them). 

The issue is when I run LVS, the errors that come up appear to be as if I did not place any of the original components. On the following link, you can see the schematic, layout and LVS errors.

https://imgur.com/a/TjRFenk

I think it may be some connections missing but I can't find where exactly.

Also, any tips on layout design are more than welcome!