Problem in importing verilog netlist to cadence

Hi,

I am using IC6.1.6 and trying to import verilog power netlist to virtuoso.

I am using File--> Import--> Verilog. My reference library contains digital cells which have pin definitions like @VDD:%:VDD!.

I am getting errors on the import  like

"Error: Can't connect "VDD!" ("[@VDD:%:VDD!]") to non-inherited terminal "VDD!"."

"Error: Can't have multiple net expressions: "[@VDD:%:VDD!]" conflicts with "[@VBP:%:VBP!]""  (VBP is also a  pin defined like @VBP:%:VBP! which is supposed to be connected to VDD!)

I am defining my Power Net Name as VDD! in Global Net Options. Do I need to specify something else as well?

Regards,

Kamran