Should I use the PIN or the NET layer for gnd?

Hi,

I have a layout of a simple PMOS transistor passing DRC, LVS and QRC by using the PIN layer MET1 purpose for the 4 terminals and the connection for the general p-substrate (community.cadence.com/.../37368).

I have some doubts about this because the gnd! connection to the p-substrate is not a PIN in my PMOS cell. How should I implement the p-substrate connection then? Maybe with the NET layer MET1 purpose?

Thanks in advanced!

David.