Declaration, Initialization and shifting real type arrays in VerilogAMS

Dear All,

I am trying to declare a real type array like:- real arr[4:0]={1,2,3,0}

Also, I tried to shift the array as arr[4:0]={arr[4:3],1.5}.

Both gives me error in verilogAMS. How we can achieve the above ? what is the right syntax to do ?

Kind Regards