Hi,
I am designing a resistive feedback TIA which needs a capacitor in its feedback loop for stability.
I would like to know the effect of a feedback capacitor on the phase margin to determine the optimal capacitance value.
My plan is to add it to the results after the stb analysis by using the direct plot>main form > phase margin (add to outputs).However it not getting added to my results list.
What could be a problem? Is there a way to add phase margin to the results using the calculator?
I also find that the gain from the stability analysis(the closed loop gain) is different from that of the gain obtained for the closed loop simulation in AC analysis. Why is the difference, how is it computed in stability analysis?
Thanks,
-Rakesh.