Hi, I am new using CADENCE, I want to create a layout with DP inside a p Silicon substrate were all my IC will behold. After I run the DRC with Assura I got the following error:
-> (SP, DP) only allowed inside ((RXHV RXHV_IBM) sized by +0.2) sized by -0.2)or in RXHV_IBM touching (text on level RXHV_IBM {NFET12MH_REV_1.0}
I try to fix this creating an RXHV over DP, but then I got this new error which I don't know how o fix:
-> RXHV with 0 or more than 1 RXHV label cadence
Can anyone help me with this problem? Thanks