Dear all,
I am currently trying to model a simple delay in VHDL-AMS.
entity DELAY is
port(
terminal vin : electrical;
terminal vout : electrical
);
end DELAY;
architecture behavioral of DELAY is
quantity vo across iout through vout to ground;
quantity vi across iin through vin to ground;
begin
vi == 1.0E12 * iin;
vo == vi'delayed(1.0E-9);
end behavioral;
However, when I try to simulate that, the input signal is not only delayed but has also a slewrate added. This is shown in the image below (green is vin and red is vout). Does anyone know where this slewrate comes from and how this can be avoided?
