Plot analog bus with non-overlayed traces in ViVa

Hi,

I do have an analog bus "vout<31:0>" and a output expression "VT("/vout<31:0>")", and I want to plot the transient signals.

In ViVa it plots all signals on top of each other (overlayed).

But I want to see each signal in a seperate trace (e.g. like in a logic analyzer).

The only way I found is to have an extra output expression for each signal, e.g. VT("/vout<0>") VT("/vout<1>") VT("/vout<2>") and so on.

But I stronlgy belief (hope) that there is a better way to plot a analog bus transient signal.

Having 16,32 or 64 bit busses and each signal its own output equation would be really annoying.

Please tell me how to plot the analog bus signals each in a seperate trace -  pleeease ;-)