Hi,
I am using Virtuoso ADE Assembler for post-layout simulation. And the version is ICADV12.3-64b.main.957.
My steps is following
1)I set "save all", ran post-layout sim (transient sim) and get the signal expression from result browser as below,
v("/i0/Xith0/Xi0/Xthpsf_combo/Xampp/Xth_psf/Xth_sw[0]/Mpassgate2[0]:SRC" ?result "tran").
2) Put the expression in "Outputs Setup", changed Output Save setup back to "Select". Reran the post-layout sim.
It showed "eval err" for that plot.
The expression of the internal node seems different from the normal output expression
The circuit is big and I will run the simulation with parameter sweep, so I want to set Output Save as "Select" to save hard disk space.
What should I do to plot the internal node signal in post-layout sim?
Thanks and regards,
Yutao