Hello everyone,
PROBLEM EXPLANATION
I am facing a strange problem. First of all, I am using ICFB (a very old version).
I have a very simple cell made of 4 transistor. This cell has a schematic view, a layout and an extracted view.
I can do simulations with the schematic view (everything work as expected) using ADE and Spice. Then, the DRC and LVS on the layout give no error.
At this point, I want to run the exact same simulation on the extracted view.
In order to do so, I go to Setup->Environment and in the Switch View List I insert "extracted" as the first element.
I then run the simulation and the result is the _exact opposite waveform_ at the output. (the block is supposed to act as a "digital" block, so I really mean that where I expect to see a "1" I get "0" and viceversa).
Now, if I check the netlists that are produced after the schematic and extracted simulations (in ADE, I go to Simulation -> Netlist -> Display Final) they don't exactly match:
A colleague suggested that I add manually pins on the layout; the point is that the pins are there both in the layout and in the extracted view. With this, I mean that if I open the extracted view, I can select the net, and the net is correctly connected to VDD! (same goes for gnd!)
Searching on google, I found someone suggesting that I put explicitly the VDD and GND pins in my symbol, so that I can connect them explicitly. I might try this, but this is not an acceptable solution for me because it would mean a redesign of a huge amount of cells. Plus, it is an already existing design, so all these simulations were done before.