Hello,

I am encountering an error when trying to characterize a DFF having asynchronous SET and RESET signals:

------------

ERROR (LIB-934): (define_arc): Ignoring arc of cell:'DFFQSRX1', r_pin:'RESETB', pin:'RESETB', type:'min_pulse_width rise_constraint' because a probe node could not be identified. Use '-probe' to specify the probe node or enable 'constraint_output_pin_mode' and rerun.

------------

I have been using the scripts from the following RAK: Using Liberate to Characterize Standard Cells(30 Mar 2017). I changed the model/netlist to use my own PDK and I have been able to characterize all my combinational cells as well as basic DFF (without any asynchronous SET/RESET signals). The problem only happens for the cells having an asynchronous signal.

I am using LIBERATE16.1.3 and SPECTRE_16.10.440.

Here is the template I use for this specific cell:

---------------

set cell DFFQBSRX1
if {[ALAPI_active_cell "DFFQBSRX1"]} {
define_cell \
-input { D } \
-clock { CLK } \
-async { SETB RESETB } \
-output { QB } \
-pinlist { CLK D QB RESETB SETB } \
-delay $delay_template_active \
-power $power_template_active \
-constraint $constraint_template_active \
$cell

}

-------------

Any help would be greatly appreciated. Thanks,

Edouard

Hello,

I am using Virtuoso version IC6.1.7.

I would like to stop the transient simulation that I perrform in ADE L by using autostop option. For that, I use an MDL file, where I define an event driven expression that would stop the transient simulation immediately after its calculation. Everything works fine normally, but I cannot use any simulation variables or outputs in MDL file. I have two questions regarding this

1) How can I use the variable that I define in ADE L window in MDL file in different expressions?

2) How can I use the output that I define in ADE L window in MDL file in different expressions?

Many thanks in advance.

Best regards,

Can

Hello, In the schematic editor, how does one enable the the auto-completion feature for the 'Library', 'Cell' and 'View' fields? Furthermore, I would like the 'View' field to default to 'symbol'. Is this possible?

Cadence Help document says "The Library, Cell, and View text fields, which can be auto-completed", but no indication of how this is actually done. My Virtuoso version: ICADV12.1-64b.500.15.2. \

Thanks,

Pritish

Hi. We have cadence installed in our lab and maintained by our support group.

Since we are the end-users, we don't have root permissions on our Cadence machine.

I'm following regularly after Cadence Hotfix/tools release and since I'm fairly experienced, I have a local installation which I use to test things before I ask our support to officially install them.

In order to do so, I mount my (remote) work directories with "mountfs". I have write permissions and I can edit files on the remote location.

Moreover, on the library manager, I can create copies of files, even on my remote file system.

However, If I try to open a remote file for edit, I get the following error:

"(SCH-1217): Could not open "x.x" for edit.

(DB-270000): dbOpenCellViewByType: Unable to lock database file for <user_directory_of_test_bench>/schematic

Essentially, I can open remote files for read only, and need to make a local copy otherwise, which misses the point.

Any hint as to why this might be happening will be helpful!

Cheers,

Matan

Hi Guys,

I can't change the size of pmos or nmos during Layout.  In my Layout "Edit Instance Properties", i don't see any "width" parameter.  Literally that does not allow me to use virtuoso for layout work properly. However in  my "Schematic editor" is working fine. Here i can change the size of nmos or pmos, based on my design requirements. 

I'm using Virtuoso 6.1.7-64b version.

Also in my CIW , during login session, i see two warnings... (cant set the value of variable 'width'    and cant set the value of variable 'height'  ). Please see the attachments for details. 

Any tips or suggestion, how to fix these issue?. 

If you guys need any additional information, please let me know.

Thanks,

John

Hi Everyone,

I've run nested sweeps in spectre and I would like to filter the data, what I postprocess and plot with OCEAN. Let's say I want to plot the results with a fixed value of the second sweep, or for a range of another sweep, or some combinations of them. I have not found any ready to use solution for that in OCEAN. I am aware of the value and famValue functions, but one can only select one value from the outer sweep.

Ideally I am looking for a function like "my_value(o_waveform "sweep_name" list(sweep_value_of_interest))" . I guess with the fam* functions one can create a multidimensional list of sweep names and values and filter that and get back the results point by point, which can be gathered into a waveform, but I feel it cumbersome (for me at least) and slow. I do not think this is the right way in OCEAN, but I do not know a better one.

Of course there is always the option to export all the data, and read it in with another program (python, matlab, etc) and do the filtering there, but there must have been an easy way to that in OCEAN.

To give a real life example why I would like to do that: I've just run some transistor characterisation simulation where I swept the gate, drain and bulk voltage relative to the source:
sw_b sweep param=VB values=[0 1 2] annotate=sweep {
sw_d sweep param=VDS start=0 stop=0.9 step=0.1 {
sw_g sweep param=VGS start=0 stop=0.9 step=0.1 {
...
}}}

Hi everyone,

I am trying to run monte carlo to test the variation of the reading time of a 1T1C DRAM cell, where the bitline cap increases by delta V. I ran a transient analysis then used the function "cross" from the calculator so that I can send a scalar expression to the Monte Carlo, the full expression is : cross(v("/net04" ?result "tran") 0.555 1 "rising" nil nil)

However, still getting this error message which states that there is no statistical data generated for the test so the Monte Carlo run stopped, any ideas what could be the problem please?

When running parametric analysis, the output waveforms are plotted as a family of curves. It is then possible to send the entire family of curves to the calculator and perform the same operation on all of them. If I have a set of traces that are not part of one family, is there a way I can send them all to the calculator at once instead of having to perform operations on each one individually?

Thanks,

Samir

Hi,

I have convergence issues even if I run very simple inverter circuit with fdsoi 28nm technology. Here I paste the schematic. As you see I tried to generate VSS=0 myself but still I have problem. Meanwhile, I paste my netlist and all the errors and warnings here.

I can not understand why I have these errors. Thank you for your help.

NETLIST

// Generated for: spectre

// Generated on: Nov 26 13:56:39 2018

// Design library name: SRAM1_13_11_2018

// Design cell name: testbench_26_11_2018

// Design view name: schematic

simulator lang=spectre

global 0 vss! VDD!

include "models.scs"

include "/home/azamolss/28nm/setup_working_dir/corners.scs"

// Library name: SRAM1_13_11_2018

// Cell name: test_26_11_2018

// View name: schematic

subckt test_26_11_2018 INPUT OUTPUT vdd vss

P0 (OUTPUT INPUT vdd vdd) lvtpfet w=80n l=30n as=6.08f ad=6.08f ps=232n \

        pd=232n nf=(1)*(1) sa=76n sb=76n sd=96n ptwell=0 par=1 sca=-1 \

        scb=-1 scc=-1 pre_layout_local=-1 p_la=0 lpccnr=0 covpccnr=0 \

        ngcon=1 wrxcnr=0 nsig_delvto_uo1=0 nsig_delvto_uo2=0 soa=1 swshe=0 \

        swrg=1 mismatch=1 m=1 xpos=-1 ypos=-1 plorient=1 plsnf=0

N0 (OUTPUT INPUT vss vss) lvtnfet w=80n l=30n as=6.08f ad=6.08f ps=232n \

        pd=232n nf=(1)*(1) sa=76n sb=76n sd=96n ptwell=0 par=1 sca=-1 \

        scb=-1 scc=-1 pre_layout_local=-1 p_la=0 lpccnr=0 covpccnr=0 \

        ngcon=1 wrxcnr=0 nsig_delvto_uo1=0 nsig_delvto_uo2=0 soa=1 swshe=0 \

        swrg=1 mismatch=1 m=1 xpos=-1 ypos=-1 plorient=1 plsnf=0

ends test_26_11_2018

// End of subcircuit definition.

// Library name: SRAM1_13_11_2018

// Cell name: testbench_26_11_2018

// View name: schematic

I6 (net7 net2 VDD! vss!) test_26_11_2018

V0 (net7 0) vsource type=pulse val0=0 val1=1

C0 (net2 0) capacitor c=50f

V3 (0 vss!) vsource dc=0 type=dc

V4 (VDD! 0) vsource dc=1 type=dc

simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \

    tnom=25 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \

    digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \

    checklimitdest=psf

tran tran stop=20n errpreset=conservative write="spectre.ic" \

    writefinal="spectre.fc" annotate=status maxiters=5

finalTimeOP info what=oppoint where=rawfile

modelParameter info what=models where=rawfile

element info what=inst where=rawfile

outputParameter info what=output where=rawfile

designParamVals info what=parameters where=rawfile

primitives info what=primitives where=rawfile

subckts info what=subckts where=rawfile

saveOptions options save=allpub subcktprobelvl=2

And here is the errors and warnings:

Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator

Version 13.1.1.117.isr8 64bit -- 19 Jun 2014

Copyright (C) 1989-2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders.

Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc.

User: azamolss   Host: venus.tele.ntnu.no   HostID: F1814302   PID: 14215

Memory  available: 132.6755 GB  physical: 135.4257 GB

CPU Type: Intel(R) Xeon(R) CPU E5-2640 0 @ 2.50GHz

          Processor PhysicalID CoreID Frequency Load

              0         0        0     2499.9     2.2

              1         1        0     2499.9     0.2

              2         0        1     2499.9     2.3

              3         1        1     2499.9     0.2

              4         0        2     2499.9     0.2

              5         1        2     2499.9     0.0

              6         0        3     2499.9     0.1

              7         1        3     2499.9     0.0

              8         0        4     2499.9     0.0

              9         1        4     2499.9     0.0

             10         0        5     2499.9     0.3

             11         1        5     2499.9     0.0

Simulating `input.scs' on venus.tele.ntnu.no at 2:08:01 PM, Mon Nov 26, 2018 (process id: 14215).

Current working directory: /home/azamolss/28nm/setup_working_dir/simulation/testbench_26_11_2018/spectre/schematic/netlist

Environment variable:

    SPECTRE_DEFAULTS=-I.

Command line:

    /eda/tools/cadence/mmsim.13/tools/bin/spectre -64 input.scs  \

        +escchars +log ../psf/spectre.out -format psfxl -raw ../psf  \

        +lqtimeout 900 -maxw 5 -maxn 5

Loading /eda/tools/cadence/mmsim.13/tools.lnx86/cmi/lib/64bit/5.0/libinfineon_sh.so ...

Loading /eda/tools/cadence/mmsim.13/tools.lnx86/cmi/lib/64bit/5.0/libphilips_o_sh.so ...

Loading /eda/tools/cadence/mmsim.13/tools.lnx86/cmi/lib/64bit/5.0/libphilips_sh.so ...

Loading /eda/tools/cadence/mmsim.13/tools.lnx86/cmi/lib/64bit/5.0/libsparam_sh.so ...

Loading /eda/tools/cadence/mmsim.13/tools.lnx86/cmi/lib/64bit/5.0/libstmodels_sh.so ...

Reading file:  /home/azamolss/28nm/setup_working_dir/simulation/testbench_26_11_2018/spectre/schematic/netlist/input.scs

Reading link:  /eda/tools/cadence/mmsim.13

Reading file:  /eda/tools/cadence/mmsim.13.11.117/tools.lnx86/spectre/etc/configs/spectre.cfg

Reading file:  /home/azamolss/28nm/setup_working_dir/simulation/testbench_26_11_2018/spectre/schematic/netlist/models.scs

Reading file:  /home/azamolss/28nm/setup_working_dir/simulation/testbench_26_11_2018/spectre/schematic/netlist/setupCornersIncludeFile.scs

Reading file:  /home/azamolss/28nm/setup_working_dir/simulation/testbench_26_11_2018/spectre/schematic/netlist/importNetlist.scs

Reading file:  /home/azamolss/28nm/setup_working_dir/corners.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/common_beol.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/common_feol.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/common_fet.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/common_varactor.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/common_varind.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/common_cmim16acc.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/common_esd.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/cmom_5u1x_2t8x_lb.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/soa.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/cmom_5u1x_2t8x_lb_wo_via.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/cmom_6u1x_2t8x_lb.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/cmom_6u1x_2t8x_lb_wo_via.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/cmom_6u1x_2u2x_2t8x_lb.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/cmom_6u1x_2u2x_2t8x_lb_wo_via.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/cmom_5u1x_1t8x_lb.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/cmom_5u1x_1t8x_lb_wo_via.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/driftotp.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/cvar_eg.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/pnpv.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/npnv.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/ind_lohq_5U1x_2T8x_LB.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/ind_hq_5U1x_2T8x_LB.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/ind_lohq_6U1x_2T8x_LB.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/ind_hq_6U1x_2T8x_LB.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/ind_lohq_6U1x_2U2x_2T8x_LB.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/ind_hq_6U1x_2U2x_2T8x_LB.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/cmim16acc.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/matching.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/rvt.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/eg.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/lsd.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/dsw.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/dsv.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/lsl.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/lsp.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/lsv.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/egncap.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/egpcap.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/rpolyp.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/rpolyh.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/rndiff.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/rnwell.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/diode.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/rmetal.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/lvt.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/eglvt.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/grhcdsti.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/grhcdgated.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/hcdgated.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/hcdsti.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/rvtnfetsb.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/egnfetsb.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/sblkndres.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/sblkpdres.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/hlvt.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/dsx.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/egext.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/cmom_rf_custom.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/veriloga.scs

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/ESD_DIODEGR.va

Reading link:  /eda/tools/cadence/mmsim.13/tools.lnx86/spectre/etc/ahdl/constants.h

Reading file:  /eda/tools/cadence/mmsim.13.11.117/tools.lnx86/spectre/etc/ahdl/constants.vams

Reading link:  /eda/tools/cadence/mmsim.13/tools.lnx86/spectre/etc/ahdl/disciplines.h

Reading file:  /eda/tools/cadence/mmsim.13.11.117/tools.lnx86/spectre/etc/ahdl/disciplines.vams

Warning from spectre during AHDL read-in.

    WARNING (VACOMP-2266): "$stop;<<--? "

        "/eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/ESD_DIODEGR.va", line 799: Cadence Verilog-A treats the $stop function as if it were a $finish. The $finish function always behaves as though the message level value is 0, regardless of the value you specify: The simulator does not report simulation time, location, or statistics about memory and CPU time usage.

    WARNING (VACOMP-2266): "$stop;<<--? "

        "/eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/ESD_DIODEGR.va", line 841: Cadence Verilog-A treats the $stop function as if it were a $finish. The $finish function always behaves as though the message level value is 0, regardless of the value you specify: The simulator does not report simulation time, location, or statistics about memory and CPU time usage.

    WARNING (VACOMP-2266): "$stop;<<--? "

        "/eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/ESD_DIODEGR.va", line 879: Cadence Verilog-A treats the $stop function as if it were a $finish. The $finish function always behaves as though the message level value is 0, regardless of the value you specify: The simulator does not report simulation time, location, or statistics about memory and CPU time usage.

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/ESD_DIODE.va

Warning from spectre during AHDL read-in.

    WARNING (VACOMP-2266): "$stop;<<--? "

        "/eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/ESD_DIODE.va", line 678: Cadence Verilog-A treats the $stop function as if it were a $finish. The $finish function always behaves as though the message level value is 0, regardless of the value you specify: The simulator does not report simulation time, location, or statistics about memory and CPU time usage.

Reading file:  /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/esdlayer.va

Warning from spectre during AHDL read-in.

    WARNING (VACOMP-2266): "$stop;<<--? "

        "/eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/esdlayer.va", line 330: Cadence Verilog-A treats the $stop function as if it were a $finish. The $finish function always behaves as though the message level value is 0, regardless of the value you specify: The simulator does not report simulation time, location, or statistics about memory and CPU time usage.

        Further occurrences of this warning will be suppressed.

Time for NDB Parsing: CPU = 1.15183 s, elapsed = 1.32661 s.

Time accumulated: CPU = 1.20382 s, elapsed = 1.32663 s.

Peak resident memory used = 52.6 Mbytes.

Reading link:  /eda/tools/cadence/mmsim.13/tools.lnx86/spectre/etc/ahdl/discipline.h

Warning from spectre in `lvtpfet':`I6.P0', in `test_26_11_2018':`I6', during hierarchy flattening.

    WARNING (SFE-30): "/eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/lvt.scs" 1453: I6.P0.lvtpfet: `swclipchk' is not a valid parameter for an instance of `utsoi2'.  Ignored.

    WARNING (SFE-30): "/eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/lvt.scs" 1453: I6.P0.lvtpfet: `pscedll' is not a valid parameter for an instance of `utsoi2'.  Ignored.

    WARNING (SFE-30): "/eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/lvt.scs" 1453: I6.P0.lvtpfet: `pscedlw' is not a valid parameter for an instance of `utsoi2'.  Ignored.

    WARNING (SFE-30): "/eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/lvt.scs" 1453: I6.P0.lvtpfet: `pncew' is not a valid parameter for an instance of `utsoi2'.  Ignored.

    WARNING (SFE-30): "/eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/lvt.scs" 1453: I6.P0.lvtpfet: `stcfl' is not a valid parameter for an instance of `utsoi2'.  Ignored.

        Further occurrences of this warning will be suppressed.

Time for Elaboration: CPU = 142.978 ms, elapsed = 143.429 ms.

Time accumulated: CPU = 1.34779 s, elapsed = 1.47051 s.

Peak resident memory used = 57.5 Mbytes.

Time for EDB Visiting: CPU = 2 ms, elapsed = 2.48098 ms.

Time accumulated: CPU = 1.35079 s, elapsed = 1.47342 s.

Peak resident memory used = 57.8 Mbytes.

Loading /eda/tools/cadence/mmsim.13/tools.lnx86/spectre/lib/64bit/mdl/libSpectreEH_sh.so ...

Global user options:

             reltol = 0.001

            vabstol = 1e-06

            iabstol = 1e-12

               temp = 27

               tnom = 25

             scalem = 1

              scale = 1

               gmin = 1e-12

             rforce = 1

           maxnotes = 5

           maxwarns = 5

             digits = 5

               cols = 80

             pivrel = 0.001

           sensfile = ../psf/sens.output

     checklimitdest = psf

               save = allpub

     subcktprobelvl = 2

               tnom = 25

             scalem = 1

              scale = 1

Circuit inventory:

              nodes 6

             iprobe 12   

             assert 56   

          capacitor 3    

           resistor 2    

             utsoi2 2    

            vsource 3    

Analysis and control statement inventory:

                 dc 1    

               info 8    

               tran 1    

Output statements:

             .probe 0    

           .measure 0    

               save 1    

Notice from spectre.

    42 warnings suppressed.

Time for parsing: CPU = 245.962 ms, elapsed = 322.604 ms.

Time accumulated: CPU = 1.59676 s, elapsed = 1.79641 s.

Peak resident memory used = 66.1 Mbytes.

~~~~~~~~~~~~~~~~~~~~~~

Pre-Simulation Summary

~~~~~~~~~~~~~~~~~~~~~~

~~~~~~~~~~~~~~~~~~~~~~

Warning from spectre.

    WARNING (SPECTRE-16707): Only tran supports psfxl format, result of other analyses will be in psfbin format.

Notice from spectre during transient analysis `tran'.

    No checklimit analysis defined for asserts. A default checklimit analysis 'SpectreChecklimitAnal' has been created with all asserts enabled.

The following asserts will be enabled for all subsequent analyses until the next checklimit analysis statement is found:

I6.P0.soa_1351 : ON

I6.P0.soa_1352 : ON

I6.P0.soa_1353 : ON

I6.P0.soa_1354 : ON

I6.P0.soa_1355 : ON

I6.P0.soa_1356 : ON

I6.P0.soa_1357 : ON

I6.P0.soa_1358 : ON

I6.P0.soa_1359 : ON

I6.P0.soa_1360 : ON

I6.P0.soa_1361 : ON

I6.P0.soa_1362 : ON

I6.P0.soa_1363 : ON

I6.P0.soa_1364 : ON

I6.P0.soa_1365 : ON

I6.P0.soa_1366 : ON

I6.P0.soa_1367 : ON

I6.P0.soa_1368 : ON

I6.P0.soa_1369 : ON

I6.P0.soa_1370 : ON

I6.P0.soa_1371 : ON

I6.P0.soa_1372 : ON

I6.P0.soa_1373 : ON

I6.P0.soa_1374 : ON

I6.P0.soa_1375 : ON

I6.P0.soa_1376 : ON

I6.P0.soa_1377 : ON

I6.P0.soa_1378 : ON

I6.N0.soa_1239 : ON

I6.N0.soa_1240 : ON

I6.N0.soa_1241 : ON

I6.N0.soa_1242 : ON

I6.N0.soa_1243 : ON

I6.N0.soa_1244 : ON

I6.N0.soa_1245 : ON

I6.N0.soa_1246 : ON

I6.N0.soa_1247 : ON

I6.N0.soa_1248 : ON

I6.N0.soa_1249 : ON

I6.N0.soa_1250 : ON

I6.N0.soa_1251 : ON

I6.N0.soa_1252 : ON

I6.N0.soa_1253 : ON

I6.N0.soa_1254 : ON

I6.N0.soa_1255 : ON

I6.N0.soa_1256 : ON

I6.N0.soa_1257 : ON

I6.N0.soa_1258 : ON

I6.N0.soa_1259 : ON

I6.N0.soa_1260 : ON

I6.N0.soa_1261 : ON

I6.N0.soa_1262 : ON

I6.N0.soa_1263 : ON

I6.N0.soa_1264 : ON

I6.N0.soa_1265 : ON

I6.N0.soa_1266 : ON

************************************************

Transient Analysis `tran': time = (0 s -> 20 ns)

************************************************

Trying `homotopy = gmin' for initial conditions.

Trying `homotopy = source' for initial conditions.

Trying `homotopy = dptran' for initial conditions..

Trying `homotopy = ptran' for initial conditions..

Trying `homotopy = arclength' for initial conditions.

None of the instantiated devices support arclength homotopy. Skipping.

Error found by spectre during IC analysis, during transient analysis `tran'.

    ERROR (SPECTRE-16385): There were 7 attempts to find the DC solution. In some of those attempts, a signal exceeded the blowup limit of its quantity. The last signal that failed is I(V4:p) = 1.58867 GA, for which the quantity is `I' and the blowup limit is (1 GA). It is possible that the circuit has no DC solution. If you really want signals this large, set the `blowup' parameter of this quantity to a larger value.

    ERROR (SPECTRE-16080): No DC solution found (no convergence). 

The values for those nodes that did not converge on the last Newton iteration are given below.  The manner in which the convergence criteria were not satisfied is also given.

            Failed test: | Value | > RelTol*Ref + AbsTol

 Top 10 Residue too large Convergence failure:

    V(I6.N0.gi) = 0 V

        residue too large: | -486.935 nA | > 43.0633 nA + 1 pA

The following set of suggestions might help you avoid convergence difficulties.  After you have a solution, write it to a nodeset file by using the `write' parameter, and read it back in on subsequent simulations by using the `readns' parameter.

1. Evaluate and resolve any notice, warning, or error messages.
2. Perform sanity check on the parameter values by using the parameter range checker (use ``+param param-limits-file'' as a command line argument) and heed any warnings. Print the minimum and maximum parameter value by using `info' analysis.  Ensure that the bounds given for instance, model, output, temperature-dependent, and operating-point (if possible) parameters are reasonable.

3. Check the direction of both independent and dependent current sources. Convergence problems might result if current sources are connected such that they force current backward through diodes.

4. Enable diagnostic messages by setting option `diagnose=detailed'.
5. Small floating resistors connected to high impedance nodes can cause convergence difficulties. Avoid very small floating resistors, particularly small parasitic resistors in semiconductors. Instead, use voltage sources or iprobes to measure current.
6. If you have an estimate of what the solution should be, use nodeset statements or a nodeset file, and set as many nodes as possible.
7. Use realistic device models. Check all component parameters, particularly nonlinear device model parameters, to ensure that they are reasonable.
8. If simulating a bipolar analog circuit, ensure that the region parameter on all transistors and diodes is set correctly.
9. Loosen tolerances, particularly absolute tolerances like `iabstol' (on options statement). If tolerances are set too tight, they might preclude convergence.
10. If the analysis fails at an extreme temperature, but succeeds at room temperature, try adding a DC analysis that sweeps temperature. Start at room temperature, sweep to the extreme temperature, and write the final solution to a nodeset file.
11. Increase the value of gmin (on options statement).
12. Use numeric pivoting in the sparse matrix factorization by setting `pivotdc=yes' (on options statement). Sometimes, it is also necessary to increase the pivot threshold to a value in the range of 0.1 to 0.5 by using `pivrel' (on options statement).
13. Try to simplify the nonlinear component models to avoid regions that might contribute to convergence problems in the model.
14. Divide the circuit into smaller pieces and simulate them individually. However, ensure that the results are close to what they would be if you had simulated the whole circuit. Use the results to generate nodesets for the whole circuit.
15. If all else fails, replace the DC analysis with a transient analysis and modify all the independent sources to start at zero and ramp to their DC values. Run transient analysis well beyond the time when all the sources have reached their final value (remember that transient analysis is very cheap when none of the signals in the circuit are changing) and write the final point to a nodeset file. To make transient analysis more efficient, set the integration method to backward Euler (`method=euler') and loosen the local truncation error criteria by increasing `lteratio', say to 50. Occasionally, this approach fails or is very slow because the circuit contains an oscillator. Often, for finding the dc solution, the oscillation can be eliminated for by setting the minimum capacitance from each node to ground (`cmin') to a large value.

Analysis `tran' was terminated prematurely due to an error.

finalTimeOP: writing operating point information to rawfile.

Error found by spectre during DC analysis, during info `finalTimeOP'.

    ERROR (SPECTRE-16041): Analysis was skipped due to inability to compute operating point.

Analysis `finalTimeOP' was terminated prematurely due to an error.

******************

DC Analysis `dcOp'

******************

Error found by spectre during DC analysis `dcOp'.

    ERROR (SPECTRE-16041): Analysis was skipped due to inability to compute operating point.

Analysis `dcOp' was terminated prematurely due to an error.

dcOpInfo: writing operating point information to rawfile.

Error found by spectre during DC analysis, during info `dcOpInfo'.

    ERROR (SPECTRE-16041): Analysis was skipped due to inability to compute operating point.

Analysis `dcOpInfo' was terminated prematurely due to an error.

modelParameter: writing model parameter values to rawfile.

element: writing instance parameter values to rawfile.

outputParameter: writing output parameter values to rawfile.

designParamVals: writing netlist parameters to rawfile.

primitives: writing primitives to rawfile.

subckts: writing subcircuits to rawfile.

Aggregate audit (2:08:04 PM, Mon Nov 26, 2018):

Time used: CPU = 2.16 s, elapsed = 3.39 s, util. = 63.8%.

Time spent in licensing: elapsed = 69.4 ms.

Peak memory used = 69.5 Mbytes.

Simulation started at: 2:08:01 PM, Mon Nov 26, 2018, ended at: 2:08:04 PM, Mon Nov 26, 2018, with elapsed time (wall clock): 3.39 s.

spectre completes with 5 errors, 11 warnings, and 2 notices.

Hi! I want to automate the plotting of sampled PNOISE and PXF results, but for these simulations the getData() function expects an argument "eventtime" (corresponding to the sampling event(s) found in the PSS run).

How can I determine the values getData() expects for "eventtime"? I tried determining them manually using the cross() and list() calculator functions, but the results don't match the string values (or list of string values?) getData() expects due to rounding / number format mismatches (e.g. for the same point the calculator returns 33.0776972388E-12, while getData() expects '3.30777e-11).

Thanks and regards,

Jorge

Hi all!

I'm having problems during VerilogA compilation and the spectre.out show me the following error in MMSIM 15.1.0.257

ERROR (VACOMP-1008): Cannot compile ahdlcmi module library.

Checking in the ahdlcmi.out file, I get the following problematic line:

ld: cannot find -lc
collect2: error: ld returned 1 exit status

Executing the same command that is contained in the ahdlcmi.out file but replacing the gcc version contained on MMSIM folder ($MMSIMHOME/tools.lnx86/cdsgcc/gcc/4.8/bin/gcc) by the gcc command available on the system, there is no longer error.

I want to know how I can redirect the gcc to be the same of the machine and not the used by Cadence

gcc version 4.8.3 (Cadence)

gcc version 4.9.2 (Linux)

Thanks!

Hello

I have designed a 16 bit adder and want to do a power supply variation and plot VDD Vs PDP. I have set up the sweep parameters alright but I can not figure out how to calculate PDP. When I try to calculate the current I get this error

*Error* ("eval" 0 t nil ("*Error* eval: not a function" IT("/R0/MINUS")))

Also when I try to calculate the propagation delay using the calculate I get 4ns, although when I can calculate visually it is much less this is the delay expression that I am using

delay(?wf1 v("/A(0)" ?result "dc"), ?value1 .6, ?edge1 "either", ?nth1 1, ?td1 0.0, ?wf2 v("/Cout" ?result "dc"), ?value2 .6, ?edge2 "either", ?nth2 1,  ?td2 0.0 , ?stop 4n, ?multiple nil)

Could you please help me with that.

I am a  student

Best regards

Hi All,

I have an extracted netlist with parasitics given by the IP provider for all standard cells. However this netlist (shown in below link, only for one cell) looks more like a .cdl than a pex.netlist. 

https://pastebin.com/Ar9iKYSK

How can I add a "Calibre View" to a cell using this netlist ? I know this can be imported as a Spice netlist to the OA library (I use IC 6.1.5), and I assume that is not accurate as parasitic resistors and capacitors in the extracted netlist will not be mapped (Calview.celmap in this case missing) to right models in PDK like what we do in PEX process.

Thanks and Regards

Anuradha

Hi,

Is there a way to change the way Viva displays the name of a hierachical net when it's plotted? For example, if a have a certain "net_X" which in my circuit is placed down in the hierarchy, eg. tb_top/IOTA/Itrimming/net_X, I would like to configure Viva to only plot "net_X" in the name field instead of the name with the full hierarchy, or even better to choose the number of levels to be used in the name starting from the net itself and going up. Is this possibile?

Thanks a lot,

Francesco 

Now, I work on the standard cell characterization with Liberate. But I don't understand the results of switching power and hidden power.

Can someone tell me why the power unit is pJ?

Can someone tell me how the liberate calculates the switching power and hidden power?

By using the power info commands,I get some information,but still don't understand.

* Cell=INVM0R_st Pin=Z RelatedPin=A RelatedPGPin=VDD Type=combinational Direction=rise_transition When= Deck= Vector_space=FR Vector_used=10
- Leakage_state =
- Leakage_value =
- Raw_equation = (((-Q(VDD))*(VDD(VDD)-GND(GND))*0.5-(((Cload(Z)*(_ecsmRailVdd - _ecsmRailGnd))*(_ecsmRailVdd - _ecsmRailGnd)*0.5))))/capacitance_unit

- Eval_equation = (((5.66381e-14)*(0.3-0)*0.5-(((1.52e-15*(0.29999-4.63108e-05))*(0.29999-4.63108e-05)*0.5))))/1e-12
- Value = 0.00842734

Can someone explain the information? 

Hi ,

We are running aging simulation with post layout netlist, and needs consume lot of memory(100GB) and hitting the queue limitation, I know that tools is saving lot of drain current for aging model generation.

I am trying to optimize the memory consumption, we are saving the voltage by probe statement

.PROBE V(ABC)

I am thinking to change it as

save ABC

will it affect memory consumption.? as probe will insert some probe instance

or if you can suggest anything to try.

Thanks,

Nasser

I recently discovered that I could relocate the legend in a VIVA plot to "inside" which was joyful for me because when it was on the left the hard copy version of the legend always took up a ridiculous amount of space and made the waveform part of the hard copy too compressed. However, when I do relocate the legend to "inside" it seems I lose the ability to click on a legend item and highlight the corresponding waveform. Is that a bug/feature, or am I doing something wrong?

Assume for now my legends are all on the left. I plot a number sinusoid waveform nodes within my circuit into strip 1 and the FFTs of them into strip 2. If I select one of the sinusoids by clicking on the legend item the corresponding waveform highlights and becomes bold/thicker so I can easily see it. However, if I select one of the FFTs by clicking on the legend the corresponding waveform does come to the front, but it is NOT thick/bold so I can easily see all of it's details. Am I doing something wrong?

Hi everyone,

i have a problem when i create CDF parameter for not gate.

this is error "ERROR (SFE-1997): "input.scs" 16: ND0.M2: parameter `w': Unknown parameter name `WP' found in expression"

i change paramter of pmos: width: [@WP:%:2u],length: [@LP:%:0.35u], same for nmos

and then i go to Tool/CDF/edit--> add CDF parameter

but when i finish, it show a warning like this:

"Warning: Warning: ams.env

Fatal: Error loading environment variables from environment file.

Terminating execution."

can you help me how to fix it? did i do wrong step to make CDF parameter?

Thank you so much.

I have been working for many years in IC5 Layout XL and loved the tool. I have worked sporadically some projects in IC  6 in the past, but this year our company decided to switch all the new projects to IC6. The new version has a lot of improvements but also I have an issue that is annoying. It happens when I move a block or when I create a bus by copying a line multiple times. Instead of keeping the connectivity, I am getting a marker over the region of the action and in the annotation browser I see a new item: "unverified connectivity area". If I right click on it and  select "extract unverified area" everything gets back to normal, but it is annoying to do it every time. I guess there is something wrong with my setup, I don't think it is something expected to happen. But all my searches came empty. Anybody can direct me on where to look or what to change to get rid of this issue ?

Thanks,

Mugurel