ADE Assembler Outputs Setup: Automatically save all nets included in expr rows

January 13, 2025, 8:35 am

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I have a bench that is currently very large and is saving all voltage nodes. I would like to only save nets that are included in the expr lines of the Outputs setup. For now I have to do this manually by clicking outputs->To Be Saved...

Is there an alternative where save commands can either be added to the outputs setup or to the netlist based on the nets contained within the expr lines?

For example, if the expr is

IDC("/ITOP/ILVL2/VDD") - IDC("/ITOP/ILVL2/VSS")

Then /ITOP/ILVL2/VDD and /ITOP/ILVL2/VSS are automatically saved.

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How to use the array index to parametrize the delay

January 13, 2025, 12:17 pm

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Hi,

I am trying to figure out how to do the following. I have an array of current sources <9:0> each of the elements of the array has a delay, which is 0*1n for the 0th element, then 1*1n for element 1, 2*1n for element 2 and so forth until element 9 which has a delay 9*1n. How can I do this parametrically so that I won't have to place manually 10 current sources. I don't want to write SKILL for that.

Thanks

Transient Analysis Terminated without error message

January 14, 2025, 10:55 pm

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Recently, I encountered an issue during a post-layout simulation. The simulation terminated with the following error message:

ERROR: Analysis terminated at user request.

Error found by spectre at time = 640.392ns during transient analysis ‘tran’ 

The error message is too brief for me to pinpoint the root cause. I didn’t manually stop the simulation, and the pre-layout simulation ran without any warnings. Additionally, the error time varies between runs. This issue has been troubling me for three weeks, and I would greatly appreciate any guidance or suggestions to resolve it.

Export assembler measurement to vcsv files

January 15, 2025, 12:09 am

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Hi,

I found a SKILL function awvSaveToCSV(), 

but it can only generate csv format files, when I need vcsv format files, is there another way to generate vcsv files through skill

Thank you!

how to start virtuoso with multi-core(cpu)?

January 16, 2025, 5:18 am

≫ Next: Unable to run PVS Quantus extraction in cds_ff_mpt (finfet 18nm)

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as the subject : how to start virtuoso with multi-core(cpu)?

Unable to run PVS Quantus extraction in cds_ff_mpt (finfet 18nm)

January 16, 2025, 1:17 pm

≫ Next: Characterizing cells with verilog-A models by liberate, but the model or instance can not be found

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Hello

I am trying to run PVS Quantus extraction on a layout that is LVS clean I have attached the images showing setup and the errors I am getting. Kindly help me how to resolve this issue.

When I checked the log file for errors it shows below error
*Error* _iliGetSlotSpecs: not a class object or class name – vfoAdvGuardRing

Please find the error log & snippets in the drive link : 

drive.google.com/drive/folders/1chjXKqf4jGhmzJkLynGA8Ig2qw1CHQIB?usp=sharing

Thank you.

Regards,

Nikhil

Characterizing cells with verilog-A models by liberate, but the model or instance can not be found

January 17, 2025, 1:34 am

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Hi, I've been trying to perform cell characterization for a basic inverter and generate a .lib file for it. The technology we used doesn't have a PMOS transistor so the schematic is implemented using nmos.

But the model or netlist could not be recognized although I have added "define_leafcell" and "extsim_deck_header" as supposed. Could someone help me please

char.tcl:

# Set the run directory. Here we use PWD, but in a distributed
# environment, it is recommended to directly specify the full path
# instead of using "PWD"
set rundir $env(PWD)

# Create the directories Liberate will write to.
exec mkdir -p ${rundir}/LDB
exec mkdir -p ${rundir}/LIBRARY
exec mkdir -p ${rundir}/DATASHEET

### Define temperature and default voltage ###
set_operating_condition -voltage 1.5 -temp 125

## Load template information for each cell ##
source ${rundir}/TEMPLATE/template_example.tcl

## Load Spice models and subckts ##
set extsim_exclusive 1
set_var extsim_deck_header ".hdl $rundir/MODELS/veriloga.va"
define_leafcell -type nmos -pin_position {0 1 2 3} {nch}
set_var extsim_model_include $rundir/MODELS/section_mos.scs

set spicefiles $rundir/MODELS/section_mos.scs
foreach cell $cells {
lappend spicefiles ${rundir}/NETLIST/${cell}.sp
}
read_spice $spicefiles

## Characterize the library for NLDM (default), CCS and ECSM timing.
char_library -ccs -ecsm -cells ${cells}

## Save characterization database for post-processing ##
write_ldb ${rundir}/LDB/example.ldb

## Generate a .lib with ccs, ecsm ###
write_library -overwrite -ccs ${rundir}/LIBRARY/example_ccs.lib
write_library -overwrite -ecsm ${rundir}/LIBRARY/example_ecsm.lib

## Generate ascii datatsheet ###
write_datasheet -format text ${rundir}/DATASHEET/example

log:

LIBERATE parameter "slew_lower_rise" set to "0.3"
LIBERATE parameter "slew_upper_rise" set to "0.7"
LIBERATE parameter "slew_lower_fall" set to "0.3"
LIBERATE parameter "slew_upper_fall" set to "0.7"
LIBERATE parameter "measure_slew_lower_rise" set to "0.3"
LIBERATE parameter "measure_slew_upper_rise" set to "0.7"
LIBERATE parameter "measure_slew_lower_fall" set to "0.3"
LIBERATE parameter "measure_slew_upper_fall" set to "0.7"
LIBERATE parameter "max_transition" set to "1.5e-09"
LIBERATE parameter "extsim_deck_header" set to ".hdl /homes/RuiLi/liberate/file/liberate/MODELS/veriloga.va"
INFO (LIB-511): (define_leafcell): Leafcell 'nch' (instance) has been identified with pin_position (0 1 2 3) mapped to (D G S B).
LIBERATE parameter "extsim_exclusive" set to "1"
LIBERATE parameter "extsim_model_include" set to "/homes/RuiLi/liberate/file/liberate/MODELS/section_mos.scs"
LIBERATE parameter "spectre_pwr" set to "0"
LIBERATE parameter "simulator" set to "ski"
LIBERATE parameter "char_library_skip_var_list" set to ""
Start Characterizing Library at (Fri Jan 17 16:56:54 CST 2025)

*Info* Removing all types
*Info* Max Shared Memory Segments : 4096
*Info* No unattached Shared Memory Segments belonging to RuiLi out of 434 total.
*Info* Max Semaphore Arrays : 128
*Info* No unattached Semaphore Arrays belonging to RuiLi out of 1 total.
*Info* Max Message Queues : 32000
*Info* No Message Queues
*Info* Zombie Process 'lsb_release' isn't 'spectre' related. Skipping.
*Info* Zombie Process 'whoami' isn't 'spectre' related. Skipping.
*Info* Zombie Process 'lsb_release' isn't 'spectre' related. Skipping.
*Info* Zombie Process 'whoami' isn't 'spectre' related. Skipping.
ERROR (LIB-926): The program will terminate because the definition of the sub-circuit or model for instance 'M0' could not be found. Run the following checks in the given sequence: the subcircuit or model is loaded, the first line in the model file is empty or has a comment, and the netlist syntax is correct. If no problem is found in these checks, use the 'define_leafcell' command to define the sub-circuit or model, and rerun Tcl

back annotating bussed terminal DC voltages with cdsterm in Symbol

January 17, 2025, 8:45 am

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Unfortunately, Cadence Forum had put this LOCK feature in the forum, so we cannot "necro post" to a question, even if we found the solution to a question thanks to the reply in the topic.

I want to replying to this post :

 Annotating bussed terminal voltages with cdsTerm() 

I found a solution to put instead of the cdsTerm("myBUS<7:0>") in the symbol label

Here is my answer :

strcat("0b" apply('strcat foreach(mapcar cds list(cdsTerm("ADJUST<7>") cdsTerm("ADJUST<6>") cdsTerm("ADJUST<5>") cdsTerm("ADJUST<4>") cdsTerm("ADJUST<3>") cdsTerm("ADJUST<2>") cdsTerm("ADJUST<1>") cdsTerm("ADJUST<0>")) sprintf(nil "%d" floor(evalstring(cds))))))

Unfortunatly, we cannot loop on index with only one name to modify, since cdsTerm will not evaluate sprintf. (mayby there is a trick with apply/eval/evalstring, but i did not try.

cdsTerm(sprintf(nil "qin7<%d>" 0)) ;=> error

Hope it helps.

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Unable to remove text labels after flattening layout pcell

January 20, 2025, 11:35 pm

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Hi,

After flattening any layout pcell (e.g., layout of a MOSFET instantiated from PDK) in LayoutXL, I am not able to select or delete the text labels that came from the pcell. Please see the screenshot below, where the instance name and cell names cannot be deleted.

Please note that all Layers and Objects are in Visible and Selectable mode, still the labels are not getting selected.

Kindly help me resolve this issue.

FYI, I have used Cadence virtuoso version IC6.1.8 - 64b.500.29. 

With regards,

ADE output for conditional string from input logic combination

January 22, 2025, 4:25 am

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Hi,

I would like to make to ADE setup and testbench more descriptive. E.g. I sweep the variables EN and Idle 0 to 1 in a corner, so 4 combinations:

      corner_Modes

EN    0 1

Idle   0 1

Note: This might be also don in a sweep, instead of within corner setup.

I would then like to have a string as ADE output too, like 00 gives "off", 11="on", 10="idle" and 01="prep-idle".
 
Is this possible directly as ADE output?

A workaround would be to introduce a string variable and to split the corner into 4 and define the string variable in the corner as separate row.

But this would not work for sweeps, only for parametric sets, and with higher add. effort.
 

I am no skill expert, but I think for an expert it should be easy and it makes the results table easier to interpret. E.g if Idd output is >1mA and string variable = "off", than I can immediately see something if wrong..

So what I need is creating a function output  from an input logic combination.

It would be also super-flexible for other things, like if specifications also depend on logic mode.

Bye Stephan

Synchronicity vs maestro view

January 22, 2025, 5:07 am

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Hi,

we use Synchronicity as version control SW. It works fine for schematics, symbols, etc. but not for maestro

E.g. you do a check-out, but still you see a green mark in Library Manager.
And if you then open it, again you will be asked if you want to check out (although you made this 10s ago).

Is there a solution to this issue?

Bye Stephan

Descend menu - Set default preferences

January 22, 2025, 6:18 am

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Hello!

When selecting signals to plot with the ADE calculator, a descend form is opened every time you need to descend into a subcell. Is there a way to avoid this by setting a env variable? I want to set it to always open for read and in a new tab.

Regards

Issue OSSPDA with xcellium AMS sim

January 23, 2025, 8:55 am

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Hi everyone, i have an issue when doing simulation with Xcellium AMS mode (spectre + xrun) the log file ends with the "OSSPDA" as the below but i dont really know the root cause of this bug 

.- when i disable the block containg the resistor, it passed the netlist creation step and go with simulation smoothly 

.- in the HED config, i dont see any HDL cellview of it, only schematic cell 

. my spectre version 19.1/ XCELLIUM ver 19.03 

Have you guys dealed with this bug already? , pleave help 
Thanks a lot. 

TM

 i attached the capture here, please have a look 
www.dropbox.com/.../bug_ams.png

analogLib/bsource component with complex coefficient

January 23, 2025, 2:05 pm

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Hello Everyone,

do you think there is a way to have a complex coefficient in the bsource component like it is shown below ? I have tried "i" and "j" , but complex numbers cannot be netlisted (I read in the forum if I am not wrong), so I am looking for any suggestion, if possible at all.

thanks 

Tommaso 

Is it possible to access design variable as parameter of systemverilog bloc

January 24, 2025, 5:23 am

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Hi everyone,

I'm doing an AMS simulation in which I want to parameterise a output generated by a systemVerilog instance . This should be used in an existing AMS simulation to enter this parameter as an input bus to the DUT.

module test_parametrized_input (Out );

output logic[63:0] Out;
parameter xValue=2;
assign Out=xValue;
endmodule

Here is the maestro view with xValue declared as a design variable:

I tryed to do as in this post in which variable is declared as a parameter with the same name than the design variable.

However it does not seem to work in ams simulation system-verilog.

Hence I wonder if it is even possible ? or must I do it in verilog-a ?

Thanks in advance for your future answer.

Best regards

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Can move component only up/down or left/right in Cadence Virtuoso

January 25, 2025, 6:54 pm

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Hello, my issue is that when I click a component and press C to copy it to another location, or M to move it, I can only move it in one direction, up/down or left/right. I have been digging through menu settings but cannot see where I can change this. Help is appreciated. 

Merge buses when creating a symbol from SpectreText netlist

January 27, 2025, 2:31 am

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Hello,

I have a netlist (constructed with an external tool) under the spectreText format. Pins are declared at different DC level in this same netlist.
I export the netlist and create a new symbol using  the button "Build a database of instances, nets and pins found in file" from the Spectre-Editor. The newly created symbol works and outputs the correct voltages but the buses are not merged. This can gives huge symbols. Is there any way to merge all the pins of the same name (A<0>, A<1>, ..., A<7>) to a single bus of the name A<7:0> ? 

Thank you,

Arthur

Maestro - problem with sweeping a transistor parameter because of netlist format

January 27, 2025, 2:30 pm

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Hello all,

When perform a designVar sweep analysis (be it in a "dc" or "ac" analysis) for the number of fingers of a transistor ("nf"), I get simulation results that do not make sense.

I was able to trace this down that each transistor macro cell has 2 netlist lines:

The 1st one containing all the basic info, gl, nf, m (not too many parameters)

And the 2nd one, where the real deep-dive netlist parameters of the said transistor exist. This 2nd line was generated as a consequence of the 1st line.

So basically when sweeping nf (number of fingers), the 2nd line of netlist will not be getting altered. Hence the wonky simulation results.

Is there an environment variable that permits the recreation of the netlist, even though the schematic does not change ?

Note: I am not sweeping the desVar through multiple corners, I doing so via the desVar sweep capability of a regular "dc" or "ac" analyses - In case I was not clear earlier.

Thank you

Frank

Cadence virtuoso version: IC23.1-64b.1SR9.24

Skill function to set x- or y-axis to linear scale

January 28, 2025, 4:04 am

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Hi,

I found following examples to set the axes to logarithmic via a skill command:

Programmatically set y-axis in VIVA in Log Scale - Custom IC Design - Cadence Technology Forums - Cadence Community

With slight modification for family plots, this works nicely.

However setting them back to linear failed. I tried several options like:

- let(((in getData("in" ?result "noise"))) drGetWaveformXVec(in)~>scale="lin" in)

- let(((in getData("in" ?result "noise"))) drGetWaveformXVec(in)~>scale="linear" in)

- let(((in getData("in" ?result "noise"))) drGetWaveformXVec(in)~>scale=nil in)

but none of them worked. What would be the right argument to achieve this?

As a background, for large testbenches with hundreds of expression, I usually write the outputs in a text editor and import them as CSV to maestro. Since the right choice of logarithmic or linear axes depends on the output dynamic range, it needs to be defined individually for each expression. This could be done very fast with a skill command/function as the one above directly when setting up the testbench.

Kind regards,

Thomas

Virtuoso Schematic shows graphically different values than query

January 29, 2025, 8:03 pm

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Hi,

I'm facing an issue with an schematic automatically generated. FET instances show different values on display than when queried. Please see pics.
The correct values are the ones shown graphically. I tried to fix this by running 'abInvokeCdfCallbacks' but the results are undesired, the values graphically were set to the ones queried.

Thanks for your help.