Dear All,

I have used $table_model() in VerilogA.

But while using it in Verilog or VerilogAMS, I am seeing errors.

So, Can we use $table_model() in verilogAMS ?

Kind Regards,

Hi,

Getting the warning message while trying to use the router in virtuoso18.1,

*WARNING* "Command wrongway_pin_escape requires application feature Router only that cannot be licensed".

*WARNING* TCL error: ERROR - no further information available.

From these two warning message what I could understand is that in virtuoso18, routing cannot be done without  "router license". Is my understanding correct?

If my understanding is not correct what are these warning messages mean?

The problem I am facing is that couldn't be routed by choosing the options "Route/Automatic Routing/All nets" as in other version of Virtuoso (6.1...).

Please suggest.

I have a simulation with a systemVerilog module and an analog block and trying to simulate them together.

1. Using ADE XL

2. Have set the simulator to ams

3. Set my connect rules

4. Made config view with AMS template

When I run, I get the error. The following is the irun logfile:

/////////////////////////

irun(64): 15.20-s049: (c) Copyright 1995-2018 Cadence Design Systems, Inc.
TOOL: irun(64) 15.20-s049: Started on Nov 10, 2020 at 11:14:18 PST
irun
-f irunArgs
-clean
-UNBUFFERED
-cdslib ./cds.lib
-noupdate
-errormax 50
-status
-nowarn DLNOHV
-nowarn DLCLAP
-v93
-incdir /ws/ld50/p41/cds/
-ade
-timescale 1ns/1ns
-vtimescale 1ns/1ns
-delay_mode None
-novitalaccl
-access r
-noparamerr
-amspartinfo ../psf/partition.info
-rnm_partinfo
-modelincdir /ws/ld50/p41/cds/
./spiceModels.scs
./amsControlSpectre.scs
-input ./probe.tcl
-run
-exit
-ncsimargs "+amsrawdir ../psf"
-spectre_args "-ahdllibdir /sim/ld50/P41_19SC800_01A_tb/offset_canc_fsm_tb/adexl/results/data/Interactive.4/sharedData/Job3/ahdl/input.ahdlSimDB"
-spectre_args +logstatus
-simcompatible_ams spectre
-name P41_19SC800_01A_tb.offset_canc_fsm_tb:config_ams
-allowredefinition
-amsbind
-top P41_19SC800_01A_tb.offset_canc_fsm_tb:schematic
-top cds_globals
./netlist.vams
./ie_card.scs
-f ./textInputs
-amscompilefile "file:/ws/ld50/p41/cds/P41_19SC800_01A_tb/adc_offset_cal/systemVerilog/verilog.sv lib:P41_19SC800_01A_tb cell:adc_offset_cal view:systemVerilog"
-makelib P41_19SC800_00A
-makelib P41_19SC800_01A
-endlib
./cds_globals.vams
-l ../psf/irun.log
-spectre_args ++aps
-spectre_args +mt=8
irun: *N,CLEAN: Removing existing directory ./INCA_libs.
file: ./netlist.vams
module P41_19SC800_01A.ref_top_v1:schematic
errors: 0, warnings: 0
module P41_19SC800_01A.adc_th_a1_cc:schematic
errors: 0, warnings: 0
module P41_19SC800_01A.adc_async_dynamic_SAR_logic_p41_v1:schematic
errors: 0, warnings: 0
module P41_19SC800_01A.adc_comparator_cap_adjust_pos:schematic
errors: 0, warnings: 0
module P41_19SC800_01A.adc_comparator_a1:schematic
errors: 0, warnings: 0
module P41_19SC800_01A.adc_core_a1_v1:schematic
errors: 0, warnings: 0
module P41_19SC800_01A_tb.offset_canc_fsm_tb:schematic
errors: 0, warnings: 0
module P41_19SC800_00A.ref_buffn:schematic
errors: 0, warnings: 0
module P41_19SC800_00A.ref_buffp:schematic
errors: 0, warnings: 0
module P41_19SC800_00A.ref_core_opamp:schematic
errors: 0, warnings: 0
module P41_19SC800_00A.ref_core:schematic
errors: 0, warnings: 0
module P41_19SC800_00A.adc_core_mom_fill:schematic
errors: 0, warnings: 0
module P41_19SC800_00A.adc_switch2:schematic
errors: 0, warnings: 0
module P41_19SC800_00A.adc_switch3:schematic
errors: 0, warnings: 0
module P41_19SC800_00A.adc_switch1:schematic
errors: 0, warnings: 0
module P41_19SC800_00A.adc_switch_array:schematic
errors: 0, warnings: 0
module P41_19SC800_00A.adc_charge_redistribution_DAC_half:schematic
errors: 0, warnings: 0
module P41_19SC800_00A.adc_charge_redistribution_DAC:schematic
errors: 0, warnings: 0
module P41_19SC800_00A.adc_async_dynamic_SAR_logic_unit1:schematic
errors: 0, warnings: 0
module P41_19SC800_00A.adc_async_dynamic_SAR_logic_delay_cell:schematic
errors: 0, warnings: 0
module P41_19SC800_00A.adc_async_dynamic_SAR_logic_unit2:schematic
errors: 0, warnings: 0
module P41_19SC800_00A.adc_async_dynamic_SAR_logic_sub:schematic
errors: 0, warnings: 0
file: ./cds_globals.vams
module worklib.cds_globals:vams
errors: 0, warnings: 0
file: /ws/ld50/p41/cds/P41_19SC800_01A_tb/adc_offset_cal/systemVerilog/verilog.sv
module P41_19SC800_01A_tb.adc_offset_cal:systemVerilog
errors: 0, warnings: 0
ncvlog: *W,SPDUSD: Include directory /ws/ld50/p41/cds/ given but not used.
Total errors/warnings found outside modules and primitives:
errors: 0, warnings: 1
ncvlog: Memory Usage - 21.3M program + 30.3M data = 51.7M total
ncvlog: CPU Usage - 0.0s system + 0.1s user = 0.1s total (0.1s, 72.7% cpu)
Caching library 'P41_19SC800_01A_tb' ....... Done
Caching library 'worklib' ....... Done
Caching library 'P41_19SC800_01A' ....... Done
Caching library 'P41_19SC800_00A' ....... Done
Elaborating the design hierarchy:
Caching library 'P41_19SC800_00A' ....... Done
Caching library 'P41_19SC800_01A' ....... Done
Caching library 'worklib' ....... Done
Top level design units:
offset_canc_fsm_tb
cds_globals
ncelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
Discipline resolution Pass...
Doing auto-insertion of connection elements...
Connect Rules applied are:
logic_cr
ncelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
Building instance overlay tables: .................... Done
Using implicit TMP libraries; associated with library P41_19SC800_01A_tb
Generating native compiled code:
P41_19SC800_01A_tb.adc_offset_cal:systemVerilog <0x00262eee>
streams: 16, words: 28830
P41_19SC800_01A_tb.offset_canc_fsm_tb:schematic <0x0340a6bf>
streams: 0, words: 0
connectLib.E2L_2:module <0x7d32c189>
streams: 9, words: 9566
connectLib.L2E_2:module <0x20ba3669>
streams: 4, words: 8893
Building instance specific data structures.
Loading native compiled code: .................... Done
Design hierarchy summary:
Instances Unique
Modules: 1386 42
Registers: 109 145
Scalar wires: 30 -
Expanded wires: 3 1
Vectored wires: 17 -
Always blocks: 88 60
Initial blocks: 15 25
Cont. assignments: 20 29
Interconnect: 412 -
Simulation timescale: 1ps
Writing initial simulation snapshot: P41_19SC800_01A_tb.offset_canc_fsm_tb:config_ams
ncelab: Memory Usage - 49.9M program + 59.9M data = 109.8M total (Peak 243.8M)
ncelab: CPU Usage - 0.1s system + 0.2s user = 0.3s total (0.5s, 60.6% cpu)
Loading snapshot P41_19SC800_01A_tb.offset_canc_fsm_tb:config_ams .................... Done
Simulating in AMS-SIE mode...
ncsim: *W,DSEM2009: This SystemVerilog design is simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
Starting analog simulation engine...
AMSD: Environment variable:
SPECTRE_DEFAULTS = -E
AMSD encountered an error: Invalid command-line arguments for spectre solver: +logstatus
See the Virtuoso AMS Designer Simulator User Guide for valid arguments of spectre solver.
ncsim: *F,RNAERR: The simulator terminated with an analog initialization error.
ncsim: Memory Usage - 38.6M program + 335.3M data = 374.0M total (374.7M Peak)
ncsim: CPU Usage - 0.1s system + 0.0s user = 0.1s total (2.1s, 3.9% cpu)
TOOL: irun(64) 15.20-s049: Exiting on Nov 10, 2020 at 11:14:35 PST (total: 00:00:17)

//////////////////////////////

It worth to mention that the same testbench is just working fine in ADE L.

Regards, Reza   

How Can I get the Skill script behind my GUI command? 

For example, from the menu bar clicking on Connectivity -> XL Probe,  I want to add a bind key for opening XL Probe.  Hence, I need to get the skill command behind this to use hiSetBindKey. Is there a way to know the history of scripts performed by the GUI?

Moreover, is there a GUI way to set shortcuts for different tools in the menu bar? 

Thanks in advance.

I would like to import my "corner setup" into ADE Assembler from a CSV file.

One of the variables defined is a file name that needs to be specified with double quotes or Cadence/Spectre will not run.

In normal CSV files, double quotes are included by escaping them with a second double quote.

However, importing the corner setup from CSV doesn't like it whether I use one, two, or three double quotes.

Is there a way to import a corner setup from CSV that supports double quotes?

This is the error I get:

ERROR (ASSEMBLER-2053): Cannot import data from the CSV file '/path/to/file/corners_test.csv' because the quotation marks used in row 8 are invalid. Ensure that the quotation marks used to enclose string values are specified in pairs. To use a quotation mark as part of a string value, enclose the string value by a pair of quotation marks and replace the quotation mark within the string with two consecutive quotation marks.

Hi Guys, I have a question about vccap in the analogue lib.

I need to simulate a design with a varying capacitor and hence use a vccap is a good choice.

However, I don't quite know how to use it and the documentation about it is a bit unclear.

May I kindly ask if anyone has ever used it before? If you don't recommend using it, may I ask if there are other possible ways of varying caps in simulation?

Thank you very much!

Mingqiang

Hi,

Assuming I have a complete test bench with timing signals, biases, voltage sources, etc connected to different sub blocks. Is there an easy way to convert this "schematic gui" into a spice level test bench? 

Thanks in advance ~ 

Is there a way in the LibManager to select multiple cells and delete them ?

Currently I only can delete one cells after the other, which is a pain if you have more than 10 cells to delete.

In my case I did a hierarchical copy between libs (which was a mistake) and need to delete the copies (~50 cells).

Hello,

I am trying to write a verilog-A model for an ideal switch that would be compatible with PSS/PNOISE simulations. 

The goal is to simulate kT/C noise in switched-capacitor circuits, so I have the switch's ON-resistance as a parameter, and I would need to also model the Ron's equivalent thermal noise when the switch is on.

The simple code below should theoretically meet that need, according to what I have read. Unfortunately, simulation results from a PSS/PNOISE analysis performed on a simple track-and-hold circuit using this code look like garbage...

If I remove the white noise term at the end of the listing, and insert resistors from analogLib in series with every switch at the schematic level, the results look OK.

I could of course do that, but I am looking for a more elegant solution, one that has thermal noise embedded within the switch model itself.

Can you please help ?

Best regards,

Marc

`include "discipline.h"
`include "constants.h"

module vA_sw1(A,B,G);

inout A, B;
input G;
electrical A, B, G;

parameter real supply=3.0, Ron=10k;

analog begin

@(cross(V(G)-supply/2, 1));
@(cross(V(G)-supply/2, -1));

I(A,B) <+ (V(G) > supply/2) * (V(A,B)/Ron + white_noise(4 * `P_K * $temperature / Ron, "thermal"));

end

endmodule

In schematic, you can change background, color or bold of wires or devices to make circuits easier to read or put it for presentation. 
Is there a similar feature for layout L?
With default coloring like this, it's almost invisible when you put it in PowerPoint.
Honestly I just do it for PowerPoint purpose only so it would be great if you have some idea for this.

(version IC 6.1.8-64b -500.8)

I am trying to extract a symbolic transfer function from a circuit I have so that I can use that transfer function in Simulink. I am designing a multi-stage op amp and wanted to be able to use the Simulink control system toolbox to optimize my op-amp and take some of the guess work out. I know how to run the XF and PZ analyses, but I'm not sure how to use them to accomplish my goals (or if I can accomplish my goals using PZ and XF). So here are my goals

Produce a symbolic expression or numerical representation of a subcircuit such that: 

1. The representation can be used to build (with the models of other subcircuits) and optimize the full circuit in Simulink
2. In addition to meeting (1), the representation convers all possible DC operating point
3. In addition to meeting (1) and (2), the representation covers the expected frequency range

I have had trouble meeting all these goals so far. XF only covers small signal analysis and I'm not sure if it actually does produce a symbolic expression. Also, with the PZ analysis, I guess I could conceivably do a frequency and voltage sweep, but I am not sure if this is any better. The PZ analysis doesn't seem to cover every frequency. So here are my questions

1. Does XF analysis produce a symbolic transfer function?
2. If XF produces such a function, how can I export it?
3. Does PZ analysiscover all input/ouput frequencies? (The name seems to imply it would)
4. If PZ does not cover all frequencies, what would be the best way to use it to generate a transfer function in Simulink (using pole-zero_block)?
5. Is cosimulation a better method? I believe I have the tools to run cosimulation.
6. If cosimulation is the best method, can someone give me directions or point me to tutorials that can be describe my specific simulation needs?

Hi, 

I have a simulation in ADE assembler where I run a transient sim first and use the final condition of the transient sim (Writefinal -->spectre.fc) as an initial condition to pss sim (readic). 

In my tran sim I have a low pass filter that I need to disable for ~300ns (using a pwl source to control) and enable after, to make sure that the filter output voltage is settled to correct value. When I run PSS sim, the tstab sims will see the PWL source in the schematic and start the tstab sim after final transition of the pwl source. So if I set the tstab time to 200ns, the total pss sim will be 300ns+200ns = 500ns. 

Is there a way to change the variable that control the filter on/off between tran/pss sim? I tried using the dynamic parameter and set the filter pwl source to transition at 1ns in pss sim, but that doesn't seem to have an effect. The pss sim logs show that its reading my parameter new value but the tstab sim still runs for 500ns. 

Here is how I am setting the filter control signal in pss sim:

Is there another way to do this? 

I can also make a run plan in Assembler and have a separate sim for tran and pss, but then I have to write the full path of the spectre.fc for pss "readic" which get cumbersome over multiple corners. 

Thanks a lot,

Hamed

Hi,

in an AMS maestro testbench, the internal vhdl variables of a digital instance should be evaluated.

This is done by a ams_sim.tcl-file, which has probe statements:
probe -create -emptyok -database ams_database {tb_xxx.DIGITAL_WRAPPER.vdhl_instance} -all -variables -memories -sc_processes -depth all
This creates a probe and saves the signals for the specified hierarchy.

The ams_sim.tcl file is included in

This works perfectly when running Single Run, Swepps and Corners. The values can be accessed in the result browser and plotted / evaluated with the calculator.

But when running Monte Carlo Sampling, the digital signals are not saved.
It's the same testbench, the only thing that changes is to switch to Monte Carlo Sampling and set the corner file for monte carlo mismatch model.

Is this a known problem?

Is there a possible workaround (maybe different method to save vhdl variables)?

Excuse me if this has been asked before but I couldn't find anything.

We have a pdk from a foundry where all the schematic symbols have the default green color.

We would like to change the color of certain symbols.

E.g, for high voltage p-cell transistors we would like the symbols to be colored purple, others, orange etc.

Is there a way to do this?

P.S we don't want to change the color based on  instances in a schematic. We want to change the color of the cell master.

Colin

hi

I transfer new pdk from CDB to OA format using the conversion toolbox. The conversion is completed without problem but
when i create a library > attach it to new pdk this error appear in icw:
*ERROR*loadcontext:
"/root/desktop/TSMC130_pdk/tsmc13rf/../skill/64bit/pdkutil.cxt"
in skill folder from newpdk there isn't any 64bit folder but there is pdkutil.cxt in skill folder
my cadance is 617-64bit and my GNU/Linux x86_64

after that when i insert object for example transistor in schematic this error is appear in icw

*Error* arrayref: can't handle nil["tsmc13rf"]
*WARNING* (SCH-1156): CDF parameter function has problem.
how can i solve it?
thanks

Dear all,

I am trying to build a C script that sets the environment, invokes the ocean software and completes the simulation without any interventions required. (basically automating the whole simulation).

In the bigger picture, I want simulations to be invoked by MATLAB and I want the simulations to be performed in inputs varying iteratively (given by a Matlab algorithm).

The C script looks something like this:

csh

source /home/install/cshrc

ocean

load("test.ocn")

The problem is that the commands up to the line "ocean" work beautifully.

But I am not able to run the "load" command and is the reason I am not able to complete the simulation.

After some searching, I found that the "load" command can be placed in a .oceanrc file. But I am not sure it will work and also I am not able to find its directory nor have any idea where to place it. 

Can anyone suggest a method so that I can complete this script?

Any leads are highly appreciated.

Thank You

Aksh Chordia

Dear all,

I am simulate a one stage amp, my mentor ask me to use PSS simulation to determine the THD and dynamic range. I use trans to check the output THD before, but don't know how to determine the dynamic range. I have been digging all day, only learn how to get the compressed -1 dB point....  Please help.

Hi

I'm using virtuoso 6.1.8 and have QRC extracting my paracitics.  I have a pretty complicated cell and I want to see what the net R and C parasitic values are on my bus - is there a way to batch export these values to CSV?  I can open it with the "Parasitics > Report Parasitics > Net" then the "Save..." button but for a bus this is kind of ...tedious. Is there a skill script or something I can use to batch export all these or the selected nets or something?

Thanks

Chris

Hi Everyone,

I need to simulate the noise of my circuit by using pnoise analysis, which is shown as below:

unsmpldNoise out 0 pnoise start=0.1 stop=10/t_period maxsideband=200
smpldNoise  out 0 pnoise start=0.1 stop=0.5/t_period maxsideband=200 \
noisetype=timedomain noisetimepoints=[3.7u 7.65u] \
numberofpoints=1

and I would like to check the noise contribution by noiseSummary function.I can get the noise contribution successfully when i transfer the result of "unsmpldNoise"(timeaverage"mode) into noiseSummary function,but I can't get the noise contribution when i transfer the result of "smpldNoise"(timedomain"mode) into noiseSummary function.

I have surveyed the discussion before( https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/36394/print-noise-summary-after-analysis-during-tran )and  the ocean script that I used is shown as below:

noiseSummary('integrated
?resultsDir "xxx.raw"
?result "smpldNoise-timedomain.pnoise"
?truncateType 'top
?truncateData 20
?from 1e3
?to 2e3
?paramValues '"7.65e-6"
?noiseUnit "V"
)

then I get the message "ERROR (OCN-6025):Value of 7.65e-6 for 'timeindex' sweep variable is not found. For further information,type ocnHelp('sweepVarValues) in the Command Interface Window (CIW).", therefore I check what value I have:  

sweepNames()
=>("timeindex" "freq")

sweepVarValues("timeindex")
=>(0.0 3.7e-06 7.65e-06)

I wonder that " 7.65e-06" is one of the value of  "timeindex" indeed, and why the message will show "Value of 7.65e-6 for 'timeindex' sweep variable is not found"? 

Or I can't use noiseSummary for pnoise "timedomain" mode?

Thanks

Guys, is there any way to scale a design (layout)? For example, let's say I have a design that includes only metal-1 and I want to scale it both in x and y directions, by a factor of 0.9. Any solution on how to do this, preferably using Virtuoso? Appreciate it.