Measurements Across Corners
Hello Im currently trying to measure the delta of the further most separated waveforms obtained by corner simulation.I have tried changing "eval type" to corners and using the peakToPeak and average...
View ArticleBindkey to activate PVS-DRC/LVS
Hi all, Is there any bindkey to set bindkey to activate PVS-DRC/LVS windows ?Thanks!
View ArticleCan harmonic balance load-pull tests be run in parallel?
Using Harmonic Balance with SpectreRF in ADE Explorer, is it possible to run load-pull simulations in parallel?By default each iteration runs sequentially regardless of the jobs setup in ADE Explorer.
View ArticleDynamic Glitch Check for gate node of a transistor
Hi,How can I report all the glitches to the gate node of a transistor?Both below statements does not seem to workdyn_glitch1 dyn_glitch node=[I0.IGCNTL.ICLK.I74.I69.MN.G] ] duration=20p...
View ArticleInstalling the license file
The following products are paid for:#INSTALLSCAPE PRODUCT "PALT812" "PALT812: Liberate AMS Client"#INSTALLSCAPE PRODUCT "PALT810" "PALT810: Liberate AMS Server"#INSTALLSCAPE PRODUCT "PALT411" "PALT411:...
View Articleclip function doesn't work for reverse DC analysis
Hi all!I want to clip a waveform which was generated by a reverse DC analysis. Unfortunately I have found that clip function doesn't work with reversed DC waveforms.Is there some workaround ? I have...
View Articlehow to enable spectre ac simulation with homotopy=dptran
there is a check box for dc simulation, no question for that part.I tried to put "homotopy=dptran" in the ac simulation->option->additionalparameters, but the ac simulation still tired "gmin" and...
View Articlehow to locate most computational extensive node/cell/circuit
hello experts, I suppose there should be some command/tool to list the computation heavy cell/circuit so designers can swap with faster behavioral models? how can I do that? IC617 + Spectre...
View ArticleLayout instances and terminals do not match the source(No layout master...
Hi,I am designing a new PDK/Tech file. Tech file is uploaded in CIW and layers looks fine in Layout suite. But when I open Layout from Schematic or generate from source, I cannot see any layout...
View ArticleFailed to initialize incremental netlisting
Hello, The log content:\o ERROR (OSSHNL-153): Failed to initialize incremental netlisting because the run directory contains\o netlist data from the previous netlisting session which has a corrupt...
View Articlefsdb to pwl
Hello,If Ihave 'fsdb' file which represents the simulations results of a simulation (waveforms), is there a way to transform it into pwl (piece wise linear) signals that I can use as stimulis ?Thanks,Kotb
View ArticleADEXL Monte Carlo simulation and dumping sim data to a txt file
Hi,I need to run MC simulation, say 100 runs, and for every single run of these 100 I want to keep saving a voltage to a text file, for ex. at the system clock and I want to do this as the simulation...
View ArticleHow to fix *WARNING* The number of errors was detected in Extract Tab: 1 in...
Hi All,I am trying to run Calibre Quantus QRC,First I make a QRC command file name "tech.def".Here is my code:DEFINE pex_tech...
View ArticleFully differential amplifier simulation setup
Dear friends, It is the first time for me to design a fully differential amplifier and I don't know know most of the simulation setup,I would like to ask you please to guide me for this simulations,I...
View ArticleAnalog low power design
I am trying to design an analog li-ion charging IC as my academic project. Is there any simple equivalent Circuit Model of Li-ion cell which I can use in virtuoso ADL simulation for transient response...
View ArticleFinding device rectangles using PVS
Hi everyone.I am trying to get the transistor shapes (i.e. rectangles) of my devices after running PVS LVS. What I can find in the generated output netlist are the X and Y coordinates. However, is...
View ArticleNo Data dialog box
Has anyone seen this before? How to get rid of this?Thanks in advance!
View ArticleSchematic check and save error
Hello,I am a newbie to this forum so excuse me for mt first question.I am getting some strange error without any explanation while performing "check and save" for my schematic on virtuoso.Error...
View ArticleGet answers to all your queries about Apple iOS Support
Apple iOS is packed with exciting features to make it a pleasurable experience for you whether you want some entertainment or wish to browse the net.However, being a technology product, iOS may develop...
View ArticleQuantus not extracting coupling capacitance between 100um traces 2um apart
Hi! How can I increase the maximum distance for capacitance extraction in Quantus?In a simple testbench I put two 100um-long metal traces (M8), and if they are 1um apart Quantus extracts the coupling...
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