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import spice net list created from calibre lvs tool
I could not read in a spice netlist into cadence and generate a schematic. The spice net list is created by Calibre LVS tool.Cadence GNU popup and tells me it created a log file a a...
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layout XL extract cellviews in hierarchy?
In Virtuoso Layout XL->Extract layout, what is the function of the Scope setting "Current Cellview and Cellviews in Hierarchy", and of the "Save Extracted Cellviews" button? Does that Scope setting...
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Accessing parameters in an SOA (asserts) file from the Virtuoso environment
Hello,I am using Safe-Operating-Area or in Cadence language "assert checks" files in an analog Virtuoso flow. I'd like to be able to program the "duration" parameter in my SOA file from within the...
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Manipulate and copy from parametric analysis plot
I am using parametric analysis to plot the curve Vout with time for different Vth values. The plot is in the figure below. The X axis is time, Y axis is voltage Vout. From the graph result, if I put a...
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Generate layout.oa for an older version of a layout (sync managed) and store...
I have DesignSync managed layouts in my library. I need to get an oa object corresponding to an older version of the layout. For example in my workspace I have layout/layout.oa for current version. I...
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noisetype_off re-ignored
Hello,Long time ago I was successfully able to disable Flicker noise using "noiseoff_type=[flicker]". This was shown in the last postings...
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question about the cdf parameters of the switch instance in analoglib
I am using the 6.1.7 version of cadence and I noticed that the switch instance in analoglib has the following cdf parameters. I was wondering if anyone could tell me why there are two fields for open...
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Monte Carlo dist=unif option
Hello,I am trying to make use of the Monte Carlo option: dist=unifwith IC6.1.7 and SPECTRE 17, but I can not find any place to choose this option.Is there a way to activate it?Kind Regards,Michael
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Check Mosfet operation region with Checks/Asserts
In ADE L I could check the mosfet operation region with the "Device Checking" Tool. I recently switched to ADE Explorer and wanted to do there the same. However I cannot get to set up the wanted check...
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Inherited Connections - connecting to nets
Hi All,I have a custom design in which (due to some reason I can't remember) I have the vdd and gnd as vdd! and gnd! (please note the exclamation!) at all levels of heirarchy. Now at the top-most...
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[Maestro] Expression to check whether an asset has been violated in a simulation
Hello people,today I have this problem, which should be easy to describe. I have a maestro view and I use it to run a simulation. This simulation includes a file which enables a huge list of asserts...
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Generate LEF file through command line
Hello,I have the GDS file of the layout. Is their any way to get the LEF file of the design through command line?
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VerilogA code error:signal exceeds blowup limit
I want to write a VerilogA model which monitors input current and prints a message if it is above certain level. I also want output to be same as input current.I wrote a model and it works but throws...
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Missing Instances - inductor (lsps_otc)
Hi,I am using lsps_otc in my design. I had added guard ring (pring) and connected it to ground.But when I run LVS it complains "missing instances" to all the lsps_otc.May I know how to connect lsps_otc...
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Generate LEF file through Script
Hello,I have the GDS file of the layout. Is their any way to get the LEF file of the design through command line or script?
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undefined function uiLoadTrigger in si.log
I can use uiLoadTrigger in CIW but si.log will complain it is undefined when do auCdl. After debugging, this error should come from libInit.il under a PDK library.Any ideas?Thanks.Fred
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spectre simulator options in spice language
I have been able to set errpreset two ways:1) command line +errpreset=conservative2) spectre tran statement: tran tran stop=20n errpreset=conservativeCan this be specified in spice format .options ?
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Running simulation on verilogAMS
Hi,I have a coworker I've been trying to help to get verilogAMS to run and to be able to run a simulation. At first verilogAMS wouldn't compile because it couldn't find the 64-bit version of ncvlog....
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error of failed request
After launch icfb, I got the following error: X Error of failed request: BadName (named color or font does not exist) Major opcode of failed request: 45 (X_OpenFont) Serial number of failed...
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Cadence Liberate Characterization Help
Hi All,For the characterization of a standard cell library, I am using LIBERATE_15.14.070 version. The cell spice model was generated using IC6.1.5, and I am using Spectre as the external simulator for...
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