Hi! I noticed in the TRAN simulation of a 4GHz clock buffer that the calculated jitter at the output differs slightly depending on which outputs are saved. If I choose to save nothing but the output clock, I get ~17fs; if I save also a drain current of one of the devices in a diff pair in the DUT, I get ~18fs, and saving the currents of both devices gives ~19fs.
I double-checked the netlists produced in all cases, and indeed the only differences are the "save" statements.
What could be causing this? Reducing the maxstep from 1ps to 0.1ps seems to solve the problem, but I was expecting that for a given maxstep the results should be consistent irrespective to the outputs saved, shouldn't them?
I'm using Spectre 17.1.0.307.isr6 64b
Thanks and regards, Jorge.