Passing a string as a design variable in ADEXL

Hello All,

I have a simulation setup where I'm writing output to a file, for post-processing; the file is created using a Verilog-A module and I have parameterized the

file name, and this all works fine in ADEL. However, when I try to run a corner sweep in ADEXL, I want to pass the output filename thru the corner setup,

in this case the input.scs contains "netlist" as an include, and the method fails.

Is there a way in ADEXL to avoid to creating a hierarchical netlist, and instead have the flat netlist as created in ADEL, i.e. not .include the netlist? or a better work around.

I would really appreciate your inputs on this issue.

Thanks,

AS