overlaping due to transition function verilogA

I have 3 ideal interleaving clock signals (zero rise and fall time, no delay) that have no overlaping.
However, after passing through the transition function in verilogA, they overlap each other at rise and fall time durations.
Does anyone have any idea to solve this problem by changing the verilogA code?

y1, y2, y3:  3 ideal interleaving clock signals

V(S4) <+ transition(y1,tdelay,trf);
V(S5) <+ transition(y2,tdelay,trf);
V(S6) <+ transition(y3,tdelay,trf);