After I get my layout from SoC Ecnounter, I wanna import it in Cadence Virtuoso to run Calibre DRC, LVS, PEX and so on. So firstly I import my std cell library (I use Nangate 45nm) then I import the Stram (my gds file) and write the library name (NangateOpenCellLibrary) and attach ASCII Tech File (technology.tf) then I hit translate.
When I go to the library to open the layout, I face this message; [There are 209 undefined packets found. Most likely, the display resource file (display.drf) for a library was not merged. To merge a display.drf file use CIW ->Tools->Display->Resource Manager->Merge Command].
What should I merge that (display.drf) with?