I have a a somewhat large circuit with an inductor. I don't set any initial condition for inductor current but from the simulation result its current is very large about 142A at the begining of the waveform.
Here is the output log file and netlist file:
Notice from spectre during topology check.
Only one connection to node `maxe'.
Circuit inventory:
nodes 28
adder 2
capacitor 3
error_controller 1
inductor 1
myComp 1
pi_controller 1
relay 4
resistor 8
soft_voltage_clamp 1
vcvs 3
vsource 7
Time for parsing: CPU = 2.999 ms, elapsed = 6.71411 ms.
Time accumulated: CPU = 185.971 ms, elapsed = 183.428 ms.
Peak resident memory used = 29.2 Mbytes.Entering remote command mode using MPSC service (spectre, ipi, v0.0, spectre0_16925_15, ).
Warning from spectre.
WARNING (SPECTRE-16707): Only tran supports psfxl format, result of other analyses will be in psfbin format.
***********************************************
Transient Analysis `tran': time = (0 s -> 5 ms)
***********************************************
DC simulation time: CPU = 2 ms, elapsed = 1.28007 ms.
Important parameter values:
start = 0 s
outputstart = 0 s
stop = 5 ms
step = 5 us
maxstep = 100 us
ic = all
useprevic = no
skipdc = no
reltol = 1e-03
abstol(V) = 1 uV
abstol(I) = 1 pA
temp = 27 C
tnom = 27 C
tempeffects = all
errpreset = moderate
method = traponly
lteratio = 3.5
relref = sigglobal
cmin = 1 pF
gmin = 1 pStran: time = 125 us (2.5 %), step = 2.453 ns (49.1 u%)
tran: time = 375 us (7.5 %), step = 1.541 ns (30.8 u%)
tran: time = 625 us (12.5 %), step = 1.541 ns (30.8 u%)
tran: time = 875 us (17.5 %), step = 1.547 ns (30.9 u%)
tran: time = 1.125 ms (22.5 %), step = 1.541 ns (30.8 u%)
tran: time = 1.375 ms (27.5 %), step = 10.5 ps (210 n%)
tran: time = 1.625 ms (32.5 %), step = 10.5 ps (210 n%)
tran: time = 1.875 ms (37.5 %), step = 1.547 ns (30.9 u%)
tran: time = 2.125 ms (42.5 %), step = 1.541 ns (30.8 u%)
tran: time = 2.375 ms (47.5 %), step = 1.546 ns (30.9 u%)
tran: time = 2.625 ms (52.5 %), step = 1.546 ns (30.9 u%)
tran: time = 2.875 ms (57.5 %), step = 1.541 ns (30.8 u%)
tran: time = 3.125 ms (62.5 %), step = 1.547 ns (30.9 u%)
tran: time = 3.375 ms (67.5 %), step = 10.5 ps (210 n%)
tran: time = 3.625 ms (72.5 %), step = 1.546 ns (30.9 u%)
tran: time = 3.875 ms (77.5 %), step = 1.541 ns (30.8 u%)
tran: time = 4.125 ms (82.5 %), step = 1.546 ns (30.9 u%)
tran: time = 4.375 ms (87.5 %), step = 10.5 ps (210 n%)
tran: time = 4.625 ms (92.5 %), step = 1.546 ns (30.9 u%)
tran: time = 4.875 ms (97.5 %), step = 1.541 ns (30.8 u%)
Number of accepted tran steps = 429252Notice from spectre during transient analysis `tran'.
Trapezoidal ringing is detected during tran analysis.
Please use method=trap for better results and performance.Initial condition solution time: CPU = 2 ms, elapsed = 1.33395 ms.
Intrinsic tran analysis time: CPU = 43.2364 s, elapsed = 43.2487 s.
Total time required for tran analysis `tran': CPU = 43.2404 s, elapsed = 43.2533 s.
Time accumulated: CPU = 46.187 s, elapsed = 47.8582 s.
Peak resident memory used = 319 Mbytes.finalTimeOP: writing operating point information to rawfile.
modelParameter: writing model parameter values to rawfile.
element: writing instance parameter values to rawfile.
outputParameter: writing output parameter values to rawfile.
designParamVals: writing netlist parameters to rawfile.
primitives: writing primitives to rawfile.
subckts: writing subcircuits to rawfile.This is the netlist:
// Generated for: spectre
// Generated on: Jun 14 14:57:00 2018
// Design library name: SIMO
// Design cell name: SIMO_boost
// Design view name: schematic
simulator lang=spectre
global 0// Library name: SIMO
// Cell name: SIMO_boost
// View name: schematic
V0 (net1 0) vsource dc=3 type=dc
V13 (vdd 0) vsource dc=1 type=dc
V12 (vref3 0) vsource dc=6 type=dc
V11 (vref1 0) vsource dc=4 type=dc
V10 (vref2 0) vsource dc=5 type=dc
V14 (clk 0) vsource type=pulse val0=0 val1=1 period=1u width=100.0n
V1 (vramp 0) vsource type=pwl pwlperiod=1u wave=[ 0 0 990n 1 1u 0 ]
I3 (vclamp vramp S1 vdd 0) myComp tdelay=0 trf=1e-12
I48 (ve2 ve1 net36) adder k1=1 k2=1
I45 (ve3 net36 pi_int) adder k1=1 k2=1
I46 (pi_out vclamp 0) soft_voltage_clamp vclamp_upper=0.8 vclamp_lower=0
I47 (pi_int pi_out) pi_controller kp=10000 ki=1
C8 (net21 0) capacitor c=10u
C7 (net28 0) capacitor c=10u
C6 (net27 0) capacitor c=10u
I2 (ve1 ve2 ve3 clk S1 s4 s5 s6 vdd 0 maxe p n) error_controller \
tdelay=1e-12 trf=1e-12 vth=0.01
R10 (Vo3 net21) resistor r=10m
R0 (Vo3 0) resistor r=20
R9 (p n) resistor r=10m
R8 (Vo2 net28) resistor r=10m
R1 (Vo2 0) resistor r=16.67
R3 (net1 net017) resistor r=10m
R7 (Vo1 net27) resistor r=10m
R2 (Vo1 0) resistor r=13.33
E7 (ve3 0 vref3 Vo3) vcvs gain=1
E5 (ve2 0 vref2 Vo2) vcvs gain=1
E3 (ve1 0 vref1 Vo1) vcvs gain=1
W14 (n Vo3 s6 0) relay vt1=400m vt2=600m ropen=1T rclosed=1m
W13 (n Vo2 s5 0) relay vt1=400m vt2=600m ropen=1T rclosed=1m
W0 (n 0 S1 0) relay vt1=400m vt2=600m ropen=1T rclosed=1m
W9 (n Vo1 s4 0) relay vt1=400m vt2=600m ropen=1T rclosed=1m
L2 (net017 p) inductor l=4.7u
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
checklimitdest=psf
tran tran stop=5m cmin=1p write="spectre.ic" writefinal="spectre.fc" \
annotate=status maxiters=5
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
save L2:1 I2:p I2:n W13:1 W9:1 W14:1 W0:1 W9:1 W9:1 W9:1 R7:1 R2:1
saveOptions options save=allpub
ahdl_include "/home3/Huan/Process/MS018/Project/SIMO/myComp/veriloga/veriloga.va"
ahdl_include "/home3/tool/IC616/tools/dfII/samples/artist/ahdlLib/adder/veriloga/veriloga.va"
ahdl_include "/home3/tool/IC616/tools/dfII/samples/artist/ahdlLib/soft_voltage_clamp/veriloga/veriloga.va"
ahdl_include "/home3/tool/IC616/tools/dfII/samples/artist/ahdlLib/pi_controller/veriloga/veriloga.va"
ahdl_include "/home3/Huan/Process/MS018/Project/SIMO/error_controller_boost_SIMO/veriloga/veriloga.va"