I am trying to perform a simple simulation with a VHDL-AMS modeled resistor. Unfortunately I cannot simulate it.
I made the following:
- Created a new Cell View in the Library Manager with the type VHDLAMSText
- Added the VHDL-AMS Code to the file and saved it via File->Extract
- Created a symbol for the resistor (resp. Virtuoso created that automatically)
- Created a new Cell View in the Library Manager with the type schematic
- Added a simple test circuit in the schematic (One source and my resistor)
- Switched to the simulator and added "ideal" to the Switch View List in the Environment options
- Tried to create the netlist Simulation->Netlist->Create
Unfortunately the following error occurs:
Netlist Error: Cannot find any info on instance "I1" in cell-view "fh_hall_elements" "test" "schematic"
Netlist Error: Some cell-views used inside this block could not be netlisted in analog context
The element I1 is my resistor.
Any ideas on how to resolve this error?
Code of the resistor:
library ieee, std;
use ieee.std_logic_1164.all;
use ieee.electrical_systems.all;
use ieee.mechanical_systems.all;
use std.textio.all;
use ieee.math_real.all;
entity myres is
port (terminal p1, p2: electrical);
end entity myres;
architecture ideal of myres is
constant R : real := 10.0e3;
quantity v across i through p1 to p2;
begin
i == v/R;
end architecture ideal;