Hello,
I am working on something and wanted to know how the cadence/spectre/spice approach to solving a circuit (especially a MOS device) changes when there is an instance of a topological change (defect). For instance, how is the nodal solution generated for a 5T op amp and how does the approach differ in the presence of a Gate-Drain or a Gate-Source short in any of the devices in the 5T? How is the solution approach in the simulator different? When solving circuits with MOS transistors, how is the conductance matrix of the circuit generated? Is this information that can be shared? Are there any reference materials you can share such that we can see how analytically the solution in any circuit (especially one with a MOS device) is modelled and solved?
The circuit simulator may approach the solution through a Newton-Raphson iterative process and if that is the case, it means that in some way the circuit simulator generates a matrix equation equivalent of the circuit. I want to understand/know how this is done for a MOS structure.
Thanks
Saikiran