I'm trying to understand what options, if any, I might have for controlling what different combinations of layers, widths, and spacing are used in a "Techgen -simulation" run. This is EXT17.12. Also if I am only planning on running Quantus-FS (field solver mode) and not the "full chip" mode (QRC), is there a way to dramatically speed up the Techgen -simulation stage?
I'm currently running:
Techgen -simulation -multi_cpu 8 -cell_off myprocess.ict
so far what I'm seeing is I wish I had the hardware to make that 8 about 128!
Thanks
-Dan