I am running high-yield estimation (HYE) simulation for custom SRAM design in Virtuoso 6.1.6 ADE XL. The simulation circuit is a critical path which contains representative cells and wire delay models to mimic 512Mb SRAM macro. We do not run a simulation directly on the 512Mb SRAM macro to avoid highly long run-time.
In HYE setup, we need to specify the sampling number for Scaled-sigma sampling (SSS) method. According to Cadence technical paper, the default number of samples for SSS is 7000.
The problem is, the 512Mb SRAM macro has millions of devices while the critical path has only hundreds of devices. When we run HYE on the critical path, we expect that the hundreds of devices' variations could mimic millions of devices' variations in some way. Assume that the default 7000 sampling number is appropriate for 512Mb SRAM macro's HYE simulation, then what sampling number is adequate for the critical path HYE simulation in order to mimic millions of devices' variations?
Actually, I am not even sure if the default 7000 sampling number is adequate when running HYE simulation directly on the 512Mb SRAM macro.
I appreciate any suggestions on this problem. Thanks and regards.