I am finishing up layout out a chip (thank God, I am done with layout!) and have four vss pads, all connected to the vss! global net on chip. In the ECAD days, I would've suffixed them with a ":" which would tell Dracula that these were virtually connected and to treat the pad pins as a common connection (all layout was manual in those dark days, no VXL). This doesn't seem to work in IC6.18, Virtuoso. VXL sees them as needing connecting. How does one handle one global net with multiple pads so that VXL is happy?
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