SystemVerilog AMS simulation (ADE) xmelab ERROR, TYCMPAT: port or terminal connection type check failed on instance (expecting datatype compatible with 'packed array' but found 'unpacked array[0:1] of packed array [3:0] of logic' instead)

packed array can't be directly connect to unpacked array. So I tried to use conversion block to connect them.

But it doesn't work for neither input or output.

Testbench #1

systemverilog inv_4b model with packed array in[3:0] and packed array out[3:0]

systemverilog inv_4b_v1 with packed by unpacked array

• input wire[3:0] in[2]
• output wire[3:0] out[2]

systemverilog packed2unpacked cell tries to convert two packed array to one packed by unpacked array

Here is the Error:

Testbench #2

systemverilog inv_4b_v2 has packed inputs (identical) and unpacked output

systemverilog unpacked2packed cell tries to convert unpacked array to packed array

Here is the ERROR:

If you have any solution to fix it, that will be very helpful. Thank you very much.