Hi
I am working on a rather large analog on top design and we've run into issues where after a certain size our LVS goes from ~10 minutes to >10 hours when we start to piece the components together. Our design has 32 individual (but repeated) channels and a control piece that is common amongst them all. We designed it to have two pieces, 16 channels each and the clump of 16 channels takes ~4 minutes to LVS (using Assura) but when we put the 2x 16 channel pieces along with this small control block (which takes ~1 minute on its own) we see it go to ~4 hours to do an LVS and even longer with more components. Is there something that we can do that's recommended to speed this up?
We're using Layout XL and it's a second generation of a design so some of the metadata used is stale (routes have stale net names on them, some routes are not named etc.) but I'm not sure if Assura uses this information or not.
The individual channels are a mosaiced piece that is designed to abut with itself and the control piece that sits between them all is its own separate instance. I have a cell that has 16 of them in a mosaic that passes LVS in ~4 minutes but that piece is not what is used in the higher level (though there isn't any reason to not use it) - in the higher level what is used is two mosaics of 16 channels and the single instance of the larger piece.
Virtuoso IC 6.1.8
Assura 4.1_USR6_EHF13
Any advice would be appreciated; thanks!
Chris