Power and delay of digital circuits using cadence

Sir,

I have some doubts. please clarify. I want to calculate various power and delay of digital circuits

1. How to calculate static power?

Suppose I use DPTL C2MOS NAND/AND logic. here A, B and Clock signal is there. for calculating static power do I make all A,B and Clock signal to 0Vdc and and annotate the current and multiply with Vdd. 

If I make A,B and clock to 1V Vdc, it gives another power. so do I add both or which is actual static power?

2. for calculating total power make A, B, Clock to pulse and and multiply Vdd and current. Is it correct?

3. how can we choose clock frequency and pulse period of A and B for delay calculation. Is there any rule to set that pulse period and run time of simulation etc.