Hi! I am experiencing issues when using @cross. In short, Spectre complains that it is enforcing very small time steps, and this makes simulations very slow (for realistic circuits).
For example, for a minimalistic circuit using the analog_mux component from ahdlLib (see netlist below), the simulator gives the messages in the excerpt below:
Warning from spectre at time = 4.625 ps during transient analysis `tran'.
WARNING (AHDLLINT-8007): "[...]/tools/dfII/samples/artist/ahdlLib/analog_mux/veriloga/veriloga.va" 45: MUX: The cross/above function in the model has imposed a time step size of (375.001 fs), which is too small and might slow down the simulation. Increase the applicable tolerances and/or expression values of the function to avoid such small step size, and for faster simulation.
Warning from spectre at time = 4.80751 ps during transient analysis `tran'.
WARNING (AHDLLINT-8007): "[...]/tools/dfII/samples/artist/ahdlLib/analog_mux/veriloga/veriloga.va" 45: MUX: The cross/above function in the model has imposed a time step size of (192.494 fs), which is too small and might slow down the simulation. Increase the applicable tolerances and/or expression values of the function to avoid such small step size, and for faster simulation.
[...]
Warning from spectre at time = 4.99846 ps during transient analysis `tran'.
WARNING (AHDLLINT-8007): "[...]/tools/dfII/samples/artist/ahdlLib/analog_mux/veriloga/veriloga.va" 45: MUX: The cross/above function in the model has imposed a time step size of (1.54391 fs), which is too small and might slow down the simulation. Increase the applicable tolerances and/or expression values of the function to avoid such small step size, and for faster simulation.
Further occurrences of this warning will be suppressed.
Warning from spectre at time = 5.00001 ps during transient analysis `tran'.
WARNING (SPECTRE-16780): LTE tolerance was temporarily relaxed to step over a discontinuity in the signal: vOUT. Check the design or use '+diagnose' to get more information.
WARNING (SPECTRE-16881): Detected possible convergence difficulties which might be related to Verilog-A models. Use the command-line option '-ahdllint=warn' to check the Verilog-A modeling issues.
[...]
The above is puzzling to me, considering that the @cross() instantiations in that component actually specify a time_tol of 1 second!:
module analog_mux(vin1, vin2, vsel, vout);
[--]
@ (cross(V(vsel) - vth, 1, 1.0, vsel.potential.abstol))
selector = 1;
@ (cross(V(vsel) - vth, -1, 1.0, vsel.potential.abstol))
selector = 0;
[--]
What is worse: it doesn't matter which time_tol value I use in my @cross() events, I always get (exactly) the same warnings/tolerance issues in my simulations, which therefore run very slow.
How can I avoid this issue? Is Spectre ignoring the time_tol argument of @cross()?
Thanks for any help!
KR, Jorge.
P.S. Spectre 20.1.0.269.isr8 64bit running in "conservative" accuracy mode (required for the target application)
Minimalistic circuit description:
simulator lang=spectre
global 0
CK (vCLK 0) vsource type=pulse val0=0 val1=1 period=1n
IN (vIN 0) vsource dc=500.0m phase=90 type=sine ampl=500.0m freq=497M
MUX (vIN 0 vCLK vOUT) analog_mux vth=0.5
LOAD (vOUT 0) capacitor c=1p
simulatorOptions options psfversion="1.4.0" reltol=1e-3 vabstol=1e-6 \
iabstol=1e-12 temp=27 tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 \
maxnotes=5 maxwarns=5 digits=5 cols=80 pivrel=1e-3 \
sensfile="../psf/sens.output" checklimitdest=psf
tran tran stop=2n errpreset=conservative write="spectre.ic" \
writefinal="spectre.fc" annotate=status maxiters=5
save vIN vCLK vOUT
ahdl_include "[...]/tools/dfII/samples/artist/ahdlLib/analog_mux/veriloga/veriloga.va"
