Stability Analysis Issue on Schematic level

Stability Analysis Issue on Schematic

Hi There,

I am  trying to run stb analysis on schematic level (pre-layout).     Breaking loop with metal resistor at one level inside 

(using IC6.1.8.64b.500.17) and ( cadence Explorer)

Following this article -

https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000tt0rEAA

This schematic is one level  down in hierarchy  >>  TOP schematic >>  loop schematic

I did verify from netlist -

I did try using name of net name ("name of top schematic"\"name of net")  in deepprobe . But,  It does not work.

Problem -  I can see from simulation results that, loop is broken at  DC analysis and   voltage on one node is 1.62V and another node is 0V. So it means that, feedback loop is broken in DC analysis