I am trying to draw the layouts for a few cells using the Virtuoso Layout Editor for which I drew the transistor level schematics using the schematic editor.
I use Connectivity ~> Generate ~> All from sources and I select 'ME1 Drawing' as the layer of the pin and 'M1_CAD TEXT' as the layer for the label. These labels are created as Labels and not Text displays.
Why 'ME1 Drawing' and 'M1_CAD TEXT' ? I went through the LVS rule decks to find this in layerDefs( "gds2" :
po_textt = textToPin( 41 type(0) )
m1_textt = textToPin( 46 type(0) )
m2_textt = textToPin( 48 type(0) )
m3_textt = textToPin( 50 type(0) )
m4_textt = textToPin( 52 type(0) )
m5_textt = textToPin( 54 type(0) )
m6_textt = textToPin( 56 type(0) )
po_text = textToPin( 100 type(0) ) ; Poly Text Layer
m1_text = textToPin( 101 type(0) ) ; Metal1 Text Layer
m2_text = textToPin( 102 type(0) ) ; Metal2 Text Layer
m3_text = textToPin( 103 type(0) ) ; Metal3 Text Layer
m4_text = textToPin( 104 type(0) ) ; MEtal4 Text Layer
m5_text = textToPin( 105 type(0) ) ; Metal5 Text Layer
m6_text = textToPin( 106 type(0) ) ; Metal6 Text Layer
and
ME1 = layer( 46 type(0) )
a few lines above.
Here's what I found in the same file but in layerDefs( "df2"
ME1= layer( "ME1" type("drawing") )
po_textt = textToPin( "PO1" type("drawing") )
m1_textt = textToPin( "ME1" type("drawing") )
m2_textt = textToPin( "ME2" type("drawing") )
m3_textt = textToPin( "ME3" type("drawing") )
m4_textt = textToPin( "ME4" type("drawing") )
m5_textt = textToPin( "ME5" type("drawing") )
m6_textt = textToPin( "ME6" type("drawing") )
po_text = textToPin( "PO1_CAD" type("TEXT") )
m1_text = textToPin( "M1_CAD" type("TEXT") )
m2_text = textToPin( "M2_CAD" type("TEXT") )
m3_text = textToPin( "M3_CAD" type("TEXT") )
m4_text = textToPin( "M4_CAD" type("TEXT") )
m5_text = textToPin( "M5_CAD" type("TEXT") )
m6_text = textToPin( "M6_CAD" type("TEXT") )
Here is the VNL Netlist that Assura generates for the schematic and the layout respectively:
Schematic netlist:
*|CDS : Assura VNL File
*|Version: 1.0
*|Date : Sat May 22 10:07:34 2021
c N_18_MM MOS D B G B S B B B ;;
* 4 pins
* 4 nets
* 0 instances
s (p D S);
e
c P_18_MM MOS D B G B S B B B ;;
* 4 pins
* 4 nets
* 0 instances
s (p D S);
e
c "XNOR2X1 schematic lowpower" Cell vdd P gnd G a I b I
y O ;;
* 5 pins
* 11 nets
* 12 instances
i M11 P_18_MM net18 a vdd vdd ; L 1.8e-07 M 1 W 3.18e-06;
i M10 P_18_MM net17 b vdd vdd ; L 1.8e-07 M 1 W 3.18e-06;
i M9 P_18_MM net39 a vdd vdd ; L 1.8e-07 M 2 W 3.18e-06;
i M8 P_18_MM net38 net18 vdd vdd ; L 1.8e-07 M 2 W 3.18e-06;
i M7 P_18_MM y net17 net38 vdd ; L 1.8e-07 M 2 W 3.18e-06;
i M6 P_18_MM y b net39 vdd ; L 1.8e-07 M 2 W 3.18e-06;
i M5 N_18_MM net18 a gnd gnd ; L 1.8e-07 M 1 W 2.4e-07;
i M4 N_18_MM net17 b gnd gnd ; L 1.8e-07 M 1 W 2.4e-07;
i M3 N_18_MM net36 b gnd gnd ; L 1.8e-07 M 1 W 4.8e-07;
i M2 N_18_MM net37 net17 gnd gnd ; L 1.8e-07 M 1 W 4.8e-07;
i M1 N_18_MM y net18 net36 gnd ; L 1.8e-07 M 1 W 4.8e-07;
i M0 N_18_MM y a net37 gnd ; L 1.8e-07 M 1 W 4.8e-07;
e
Layout netlist:
*|CDS : Assura VNL File
*|Version: 1.0
*|Date : Sat May 22 10:07:55 2021
c N_18_MM MOS D NONE G NONE S NONE B NONE;;
* 4 pins
* 4 nets
* 0 instances
e
c P_18_MM MOS D NONE G NONE S NONE B NONE;;
* 4 pins
* 4 nets
* 0 instances
e
c "XNOR2X1 layout lowpower" Cell;;
* 0 pins
* 51 nets
* 16 instances
i avD27_1 N_18_MM avC25 avS36 avC23 avS191; l 1.8e-07 w 2.4e-07;
i avD27_2 N_18_MM avC33 avS34 avC31 avS191; l 1.8e-07 w 4.8e-07;
i avD27_3 N_18_MM avC29 avS35 avC27 avS191; l 1.8e-07 w 4.8e-07;
i avD27_4 N_18_MM avC32 avS37 avC30 avS191; l 1.8e-07 w 4.8e-07;
i avD27_5 N_18_MM avC28 avS38 avC26 avS191; l 1.8e-07 w 4.8e-07;
i avD27_6 N_18_MM avC24 avS40 avC22 avS191; l 1.8e-07 w 2.4e-07;
i avD28_1 P_18_MM avC6 avS39 avC7 avS196; l 1.8e-07 w 3.18e-06;
i avD28_2 P_18_MM avC8 avS41 avC9 avS194; l 1.8e-07 w 3.18e-06;
i avD28_3 P_18_MM avC9 avS42 avC10 avS194; l 1.8e-07 w 3.18e-06;
i avD28_4 P_18_MM avC11 avS43 avC12 avS192; l 1.8e-07 w 3.18e-06;
i avD28_5 P_18_MM avC12 avS44 avC13 avS192; l 1.8e-07 w 3.18e-06;
i avD28_6 P_18_MM avC14 avS45 avC15 avS195; l 1.8e-07 w 3.18e-06;
i avD28_7 P_18_MM avC15 avS46 avC16 avS195; l 1.8e-07 w 3.18e-06;
i avD28_8 P_18_MM avC17 avS47 avC18 avS193; l 1.8e-07 w 3.18e-06;
i avD28_9 P_18_MM avC18 avS48 avC19 avS193; l 1.8e-07 w 3.18e-06;
i avD28_10 P_18_MM avC20 avS49 avC21 avS197; l 1.8e-07 w 3.18e-06;
e
Notice how the netlist for the layout cell says "0 pins"
Here's the layers in which they are present:
Here's what the report generated by Assura says:
This was initially resolved with a customer support personnel from imec (europractice) for the other cells, yes what I mean to tell is this configuration works absolutely fine for a few other cells.
I am clueless as to how Assura isn't ale to detect the pins. Here's what Layout XL says:
Can someone tell me what could be going wrong?