Hi all,
until now I was simulating with a SP file which was compressed during the simulation, like the log files shows
**********************************************************************************************************************************
Reading file: /projects/ibm/csoi8sw/QM77180/work_libs/tfant/cds/04_snp/es2lam_evb/v10_reduced.s542p
Notice from spectre during hierarchy flattening.
nport instance NPORT0 has 348 unused ports formed between: (HBLNA1_OMN_block_se, 0),(HBLNA1_OMN_Ctune, 0),(HBLNA1_OMN_Decoup0, 0),(HBLNA1_OMN_Decoup1, 0),(HBLNA1_OMN_Decoup2, 0),(HBLNA1_OMN_ESD, 0),(HBLNA1_OMN_Ldrain, 0),(HBLNA1_OMN_vddRes, 0),(HBLNA1_unit1_byp_C1, 0),(HBLNA1_unit1_byp_C2, 0),(HBLNA1_unit1_byp_se1, 0),(HBLNA1_unit1_byp_se2, 0),(HBLNA1_unit1_byp_sh, 0),(HBLNA1_unit1_cg_ds, 0),(HBLNA1_unit1_cg_gs, 0),(HBLNA1_unit1_cgbias_C, 0),(HBLNA1_unit1_cgbias_CR, 0),(HBLNA1_unit1_cgbias_iref, 0),(HBLNA1_unit1_cgbias_res, 0),(HBLNA1_unit1_cgbias_vbias, 0),(HBLNA1_unit1_Cs, 0),(HBLNA1_unit1_cs_ds, 0),(HBLNA1_unit1_cs_gs, 0),(HBLNA1_unit1_csbias_C, 0),(HBLNA1_unit1_csbias_cg_iref, 0),(HBLNA1_unit1_csbias_cs_iref, 0),(HBLNA1_unit1_csbias_R, 0),(HBLNA1_unit1_csbias_vbias, 0),(HBLNA1_unit1_drainZ, 0),(HBLNA1_unit1_inputSH_ESD, 0),(HBLNA1_unit2_byp_C1, 0),(HBLNA1_unit2_byp_C2, 0),(HBLNA1_unit2_byp_se1, 0),(HBLNA1_unit2_byp_se2, 0),(HBLNA1_unit2_byp_sh, 0),(HBLNA1_unit2_cg_ds, 0),(HBLNA1_unit2_cg_gs, 0),(HBLNA1_unit2_cgbias_C, 0),(HBLNA1_unit2_cgbias_CR, 0),(HBLNA1_unit2_cgbias_iref, 0),(HBLNA1_unit2_cgbias_res, 0),(HBLNA1_unit2_cgbias_vbias, 0),(HBLNA1_unit2_Cs, 0),(HBLNA1_unit2_cs_ds, 0),(HBLNA1_unit2_cs_gs, 0),(HBLNA1_unit2_csbias_C, 0),(HBLNA1_unit2_csbias_cg_iref, 0),(HBLNA1_unit2_csbias_cs_iref, 0),(HBLNA1_unit2_csbias_R, 0),(HBLNA1_unit2_csbias_vbias, 0),(HBLNA1_unit2_drainZ, 0),(HBLNA1_unit2_inputSH_ESD, 0),(HBLNA1_unit3_byp_C1, 0),(HBLNA1_unit3_byp_C2, 0),(HBLNA1_unit3_byp_se1, 0),(HBLNA1_unit3_byp_se2, 0),(HBLNA1_unit3_byp_sh, 0),(HBLNA1_unit3_cg_ds, 0),(HBLNA1_unit3_cg_gs, 0),(HBLNA1_unit3_cgbias_C, 0),(HBLNA1_unit3_cgbias_cg_iref, 0),(HBLNA1_unit3_cgbias_res, 0),(HBLNA1_unit3_Cs, 0),(HBLNA1_unit3_cs_ds, 0),(HBLNA1_unit3_cs_gs, 0),(HBLNA1_unit3_csbias_C, 0),(HBLNA1_unit3_csbias_cg_iref, 0),(HBLNA1_unit3_csbias_cs_iref, 0),(HBLNA1_unit3_csbias_vbias, 0),(HBLNA1_unit3_drainZ, 0),(HBLNA1_unit3_inputSH_ESD, 0),(HBLNA1_unit3_Ldeg, 0),(HBLNA1_unit12_Ldeg, 0),(MBLNA1_OMN_block_se, 0),(MBLNA1_OMN_Ctune, 0),(MBLNA1_OMN_Decoup0, 0),(MBLNA1_OMN_Decoup1, 0),(MBLNA1_OMN_Decoup2, 0),(MBLNA1_OMN_drain_res, 0),(MBLNA1_OMN_ESD, 0),(MBLNA1_OMN_Ldrain, 0),(MBLNA1_OMN_vddRes, 0),(MBLNA1_unit1_byp_C1, 0),(MBLNA1_unit1_byp_C2, 0),(MBLNA1_unit1_byp_se1, 0),(MBLNA1_unit1_byp_se2, 0),(MBLNA1_unit1_byp_sh, 0),(MBLNA1_unit1_cg_ds, 0),(MBLNA1_unit1_cg_gs, 0),(MBLNA1_unit1_cgbias_C, 0),(MBLNA1_unit1_cgbias_CR, 0),(MBLNA1_unit1_cgbias_iref, 0),(MBLNA1_unit1_cgbias_res, 0),(MBLNA1_unit1_cgbias_vbias, 0),(MBLNA1_unit1_Cs, 0),(MBLNA1_unit1_cs_ds, 0),(MBLNA1_unit1_cs_gs, 0),(MBLNA1_unit1_csbias_C, 0),(MBLNA1_unit1_csbias_cg_iref, 0),(MBLNA1_unit1_csbias_cs_iref, 0),(MBLNA1_unit1_csbias_R, 0),(MBLNA1_unit1_csbias_vbias, 0),(MBLNA1_unit1_drainZ, 0),(MBLNA1_unit1_inputSH_ESD, 0),(MBLNA1_unit2_byp_C1, 0),(MBLNA1_unit2_byp_C2, 0),(MBLNA1_unit2_byp_se1, 0),(MBLNA1_unit2_byp_se2, 0),(MBLNA1_unit2_byp_sh, 0),(MBLNA1_unit2_cg_ds, 0),(MBLNA1_unit2_cg_gs, 0),(MBLNA1_unit2_cgbias_C, 0),(MBLNA1_unit2_cgbias_CR, 0),(MBLNA1_unit2_cgbias_iref, 0),(MBLNA1_unit2_cgbias_res, 0),(MBLNA1_unit2_cgbias_vbias, 0),(MBLNA1_unit2_Cs, 0),(MBLNA1_unit2_cs_ds, 0),(MBLNA1_unit2_cs_gs, 0),(MBLNA1_unit2_csbias_C, 0),(MBLNA1_unit2_csbias_cg_iref, 0),(MBLNA1_unit2_csbias_cs_iref, 0),(MBLNA1_unit2_csbias_R, 0),(MBLNA1_unit2_csbias_vbias, 0),(MBLNA1_unit2_drainZ, 0),(MBLNA1_unit2_inputSH_ESD, 0),(MBLNA1_unit3_byp_C1, 0),(MBLNA1_unit3_byp_C2, 0),(MBLNA1_unit3_byp_se1, 0),(MBLNA1_unit3_byp_se2, 0),(MBLNA1_unit3_byp_sh, 0),(MBLNA1_unit3_cg_ds, 0),(MBLNA1_unit3_cg_gs, 0),(MBLNA1_unit3_cgbias_C, 0),(MBLNA1_unit3_cgbias_cg_iref, 0),(MBLNA1_unit3_cgbias_res, 0),(MBLNA1_unit3_Cs, 0),(MBLNA1_unit3_cs_ds, 0),(MBLNA1_unit3_cs_gs, 0),(MBLNA1_unit3_csbias_C, 0),(MBLNA1_unit3_csbias_cg_iref, 0),(MBLNA1_unit3_csbias_cs_iref, 0),(MBLNA1_unit3_csbias_vbias, 0),(MBLNA1_unit3_drainZ, 0),(MBLNA1_unit3_inputSH_ESD, 0),(MBLNA1_unit3_Ldeg, 0),(MBLNA1_unit12_Ldeg, 0),(MBLNA2_OMN_block_se, 0),(MBLNA2_OMN_Ctune, 0),(MBLNA2_OMN_Decoup0, 0),(MBLNA2_OMN_Decoup1, 0),(MBLNA2_OMN_Decoup2, 0),(MBLNA2_OMN_drain_res, 0),(MBLNA2_OMN_ESD, 0),(MBLNA2_OMN_Ldrain, 0),(MBLNA2_OMN_vddRes, 0),(MBLNA2_unit1_byp_C1, 0),(MBLNA2_unit1_byp_C2, 0),(MBLNA2_unit1_byp_se1, 0),(MBLNA2_unit1_byp_se2, 0),(MBLNA2_unit1_byp_sh, 0),(MBLNA2_unit1_cg_ds, 0),(MBLNA2_unit1_cg_gs, 0),(MBLNA2_unit1_cgbias_C, 0),(MBLNA2_unit1_cgbias_CR, 0),(MBLNA2_unit1_cgbias_iref, 0),(MBLNA2_unit1_cgbias_res, 0),(MBLNA2_unit1_cgbias_vbias, 0),(MBLNA2_unit1_Cs, 0),(MBLNA2_unit1_cs_ds, 0),(MBLNA2_unit1_cs_gs, 0),(MBLNA2_unit1_csbias_C, 0),(MBLNA2_unit1_csbias_cg_iref, 0),(MBLNA2_unit1_csbias_cs_iref, 0),(MBLNA2_unit1_csbias_R, 0),(MBLNA2_unit1_csbias_vbias, 0),(MBLNA2_unit1_drainZ, 0),(MBLNA2_unit1_inputSH_ESD, 0),(MBLNA2_unit2_byp_C1, 0),(MBLNA2_unit2_byp_C2, 0),(MBLNA2_unit2_byp_se1, 0),(MBLNA2_unit2_byp_se2, 0),(MBLNA2_unit2_byp_sh, 0),(MBLNA2_unit2_cg_ds, 0),(MBLNA2_unit2_cg_gs, 0),(MBLNA2_unit2_cgbias_C, 0),(MBLNA2_unit2_cgbias_CR, 0),(MBLNA2_unit2_cgbias_iref, 0),(MBLNA2_unit2_cgbias_res, 0),(MBLNA2_unit2_cgbias_vbias, 0),(MBLNA2_unit2_Cs, 0),(MBLNA2_unit2_cs_ds, 0),(MBLNA2_unit2_cs_gs, 0),(MBLNA2_unit2_csbias_C, 0),(MBLNA2_unit2_csbias_cg_iref, 0),(MBLNA2_unit2_csbias_cs_iref, 0),(MBLNA2_unit2_csbias_R, 0),(MBLNA2_unit2_csbias_vbias, 0),(MBLNA2_unit2_drainZ, 0),(MBLNA2_unit2_inputSH_ESD, 0),(MBLNA2_unit3_byp_C1, 0),(MBLNA2_unit3_byp_C2, 0),(MBLNA2_unit3_byp_se1, 0),(MBLNA2_unit3_byp_se2, 0),(MBLNA2_unit3_byp_sh, 0),(MBLNA2_unit3_cg_ds, 0),(MBLNA2_unit3_cg_gs, 0),(MBLNA2_unit3_cgbias_C, 0),(MBLNA2_unit3_cgbias_cg_iref, 0),(MBLNA2_unit3_cgbias_res, 0),(MBLNA2_unit3_Cs, 0),(MBLNA2_unit3_cs_ds, 0),(MBLNA2_unit3_cs_gs, 0),(MBLNA2_unit3_csbias_C, 0),(MBLNA2_unit3_csbias_cg_iref, 0),(MBLNA2_unit3_csbias_cs_iref, 0),(MBLNA2_unit3_csbias_vbias, 0),(MBLNA2_unit3_drainZ, 0),(MBLNA2_unit3_inputSH_ESD, 0),(MBLNA2_unit3_Ldeg, 0),(MBLNA2_unit12_Ldeg, 0),(MBLNA3_OMN_block_se, 0),(MBLNA3_OMN_Ctune, 0),(MBLNA3_OMN_Decoup0, 0),(MBLNA3_OMN_Decoup1, 0),(MBLNA3_OMN_Decoup2, 0),(MBLNA3_OMN_ESD, 0),(MBLNA3_OMN_Ldrain, 0),(MBLNA3_OMN_vddRes, 0),(MBLNA3_unit1_byp_C1, 0),(MBLNA3_unit1_byp_C2, 0),(MBLNA3_unit1_byp_se1, 0),(MBLNA3_unit1_byp_se2, 0),(MBLNA3_unit1_byp_sh, 0),(MBLNA3_unit1_cg_ds, 0),(MBLNA3_unit1_cg_gs, 0),(MBLNA3_unit1_cgbias_C, 0),(MBLNA3_unit1_cgbias_CR, 0),(MBLNA3_unit1_cgbias_iref, 0),(MBLNA3_unit1_cgbias_res, 0),(MBLNA3_unit1_cgbias_vbias, 0),(MBLNA3_unit1_Cs, 0),(MBLNA3_unit1_cs_ds, 0),(MBLNA3_unit1_cs_gs, 0),(MBLNA3_unit1_csbias_C, 0),(MBLNA3_unit1_csbias_cg_iref, 0),(MBLNA3_unit1_csbias_cs_iref, 0),(MBLNA3_unit1_csbias_R, 0),(MBLNA3_unit1_csbias_vbias, 0),(MBLNA3_unit1_drainZ, 0),(MBLNA3_unit1_inputSH_ESD, 0),(MBLNA3_unit2_byp_C1, 0),(MBLNA3_unit2_byp_C2, 0),(MBLNA3_unit2_byp_se1, 0),(MBLNA3_unit2_byp_se2, 0),(MBLNA3_unit2_byp_sh, 0),(MBLNA3_unit2_cg_ds, 0),(MBLNA3_unit2_cg_gs, 0),(MBLNA3_unit2_cgbias_C, 0),(MBLNA3_unit2_cgbias_CR, 0),(MBLNA3_unit2_cgbias_iref, 0),(MBLNA3_unit2_cgbias_res, 0),(MBLNA3_unit2_cgbias_vbias, 0),(MBLNA3_unit2_Cs, 0),(MBLNA3_unit2_cs_ds, 0),(MBLNA3_unit2_cs_gs, 0),(MBLNA3_unit2_csbias_C, 0),(MBLNA3_unit2_csbias_cg_iref, 0),(MBLNA3_unit2_csbias_cs_iref, 0),(MBLNA3_unit2_csbias_R, 0),(MBLNA3_unit2_csbias_vbias, 0),(MBLNA3_unit2_drainZ, 0),(MBLNA3_unit2_inputSH_ESD, 0),(MBLNA3_unit3_byp_C1, 0),(MBLNA3_unit3_byp_C2, 0),(MBLNA3_unit3_byp_se1, 0),(MBLNA3_unit3_byp_se2, 0),(MBLNA3_unit3_byp_sh, 0),(MBLNA3_unit3_cg_ds, 0),(MBLNA3_unit3_cg_gs, 0),(MBLNA3_unit3_cgbias_C, 0),(MBLNA3_unit3_cgbias_cg_iref, 0),(MBLNA3_unit3_cgbias_res, 0),(MBLNA3_unit3_Cs, 0),(MBLNA3_unit3_cs_ds, 0),(MBLNA3_unit3_cs_gs, 0),(MBLNA3_unit3_csbias_C, 0),(MBLNA3_unit3_csbias_cg_iref, 0),(MBLNA3_unit3_csbias_cs_iref, 0),(MBLNA3_unit3_csbias_vbias, 0),(MBLNA3_unit3_drainZ, 0),(MBLNA3_unit3_inputSH_ESD, 0),(MBLNA3_unit3_Ldeg, 0),(MBLNA3_unit12_Ldeg, 0),(MLBLNA_OMN_block_se, 0),(MLBLNA_OMN_Ctune, 0),(MLBLNA_OMN_Decoup0, 0),(MLBLNA_OMN_Decoup1, 0),(MLBLNA_OMN_ESD, 0),(MLBLNA_OMN_Ldrain, 0),(MLBLNA_OMN_vddRes, 0),(MLBLNA_unit1_byp_C1, 0),(MLBLNA_unit1_byp_C2, 0),(MLBLNA_unit1_byp_se1, 0),(MLBLNA_unit1_byp_se2, 0),(MLBLNA_unit1_byp_sh, 0),(MLBLNA_unit1_cg_ds, 0),(MLBLNA_unit1_cg_gs, 0),(MLBLNA_unit1_cgbias_C, 0),(MLBLNA_unit1_cgbias_CR, 0),(MLBLNA_unit1_cgbias_iref, 0),(MLBLNA_unit1_cgbias_res, 0),(MLBLNA_unit1_cgbias_vbias, 0),(MLBLNA_unit1_Cs, 0),(MLBLNA_unit1_cs_ds, 0),(MLBLNA_unit1_cs_gs, 0),(MLBLNA_unit1_csbias_C, 0),(MLBLNA_unit1_csbias_cg_iref, 0),(MLBLNA_unit1_csbias_cs_iref, 0),(MLBLNA_unit1_csbias_R, 0),(MLBLNA_unit1_csbias_vbias, 0),(MLBLNA_unit1_drainZ, 0),(MLBLNA_unit1_inputSH_ESD, 0),(MLBLNA_unit2_byp_C1, 0),(MLBLNA_unit2_byp_C2, 0),(MLBLNA_unit2_byp_se1, 0),(MLBLNA_unit2_byp_se2, 0),(MLBLNA_unit2_byp_sh, 0),(MLBLNA_unit2_cg_ds, 0),(MLBLNA_unit2_cg_gs, 0),(MLBLNA_unit2_cgbias_C, 0),(MLBLNA_unit2_cgbias_CR, 0),(MLBLNA_unit2_cgbias_iref, 0),(MLBLNA_unit2_cgbias_res, 0),(MLBLNA_unit2_cgbias_vbias, 0),(MLBLNA_unit2_Cs, 0),(MLBLNA_unit2_cs_ds, 0),(MLBLNA_unit2_cs_gs, 0),(MLBLNA_unit2_csbias_C, 0),(MLBLNA_unit2_csbias_cg_iref, 0),(MLBLNA_unit2_csbias_cs_iref, 0),(MLBLNA_unit2_csbias_R, 0),(MLBLNA_unit2_csbias_vbias, 0),(MLBLNA_unit2_drainZ, 0),(MLBLNA_unit2_inputSH_ESD, 0),(MLBLNA_unit12_Ldeg, 0),(0, 0),(0, 0).
To make the simulation more efficient, original S-parameters data file
/projects/ibm/csoi8sw/QM77180/work_libs/tfant/cds/04_snp/es2lam_evb/v10_reduced.s542p
has been compressed to
/scratch/tfant/simulation/QM77180_tb/tb_em_fullchip_v3/maestro/results/maestro/Interactive.75/1/die01_hb2/netlist/v10_reduced_compressed_1.s194p
with no loss of accuracy. This operation is equivalent to replacing, in the flat version of the netlist, the original instance line with the following:
NPORT0( 4000A_EVB_EM_LNA_v2_LNA_AUX_1 0 4000A_EVB_EM_LNA_v2_LNA_AUX_2 0 4000A_EVB_EM_LNA_v2_LNA_AUX_3 0 4000A_EVB_EM_LNA_v2_LNA_AUX_4 0 4000A_EVB_EM_LNA_v2_LNA_AUX_LMB 0 4000A_EVB_EM_LNA_v2_LNA_AUX_MB 0 HBLNA1_unit1_csbias_cg_iref_IDAC 0 HBLNA1_unit1_csbias_cs_iref_IDAC 0 HBLNA1_unit2_csbias_cg_iref_IDAC 0 HBLNA1_unit2_csbias_cs_iref_IDAC 0 HBLNA1_unit3_csbias_cg_iref_IDAC 0 HBLNA1_unit3_csbias_cs_iref_IDAC 0 HBLNA2_OMN_block_se 0 HBLNA2_OMN_Ctune 0 HBLNA2_OMN_Decoup0 0 HBLNA2_OMN_Decoup1 0 HBLNA2_OMN_ESD 0 HBLNA2_OMN_Ldrain 0 HBLNA2_OMN_vddRes 0 HBLNA2_unit1_byp_C1 0 HBLNA2_unit1_byp_C2 0 HBLNA2_unit1_byp_se1 0 HBLNA2_unit1_byp_se2 0 HBLNA2_unit1_byp_sh 0 HBLNA2_unit1_cg_ds 0 HBLNA2_unit1_cg_gs 0 HBLNA2_unit1_cgbias_C 0 HBLNA2_unit1_cgbias_CR 0 HBLNA2_unit1_cgbias_iref 0 HBLNA2_unit1_cgbias_res 0 HBLNA2_unit1_cgbias_vbias 0 HBLNA2_unit1_Cs 0 HBLNA2_unit1_cs_ds 0 HBLNA2_unit1_cs_gs 0 HBLNA2_unit1_csbias_C 0 HBLNA2_unit1_csbias_cg_iref 0 HBLNA2_unit1_csbias_cg_iref_IDAC 0 HBLNA2_unit1_csbias_cs_iref 0 HBLNA2_unit1_csbias_cs_iref_IDAC 0 HBLNA2_unit1_csbias_R 0 HBLNA2_unit1_csbias_vbias 0 HBLNA2_unit1_drainZ 0 HBLNA2_unit1_inputSH_ESD 0 HBLNA2_unit2_byp_C1 0 HBLNA2_unit2_byp_C2 0 HBLNA2_unit2_byp_se1 0 HBLNA2_unit2_byp_se2 0 HBLNA2_unit2_byp_sh 0 HBLNA2_unit2_cg_ds 0 HBLNA2_unit2_cg_gs 0 HBLNA2_unit2_cgbias_C 0 HBLNA2_unit2_cgbias_CR 0 HBLNA2_unit2_cgbias_iref 0 HBLNA2_unit2_cgbias_res 0 HBLNA2_unit2_cgbias_vbias 0 HBLNA2_unit2_Cs 0 HBLNA2_unit2_cs_ds 0 HBLNA2_unit2_cs_gs 0 HBLNA2_unit2_csbias_C 0 HBLNA2_unit2_csbias_cg_iref 0 HBLNA2_unit2_csbias_cg_iref_IDAC 0 HBLNA2_unit2_csbias_cs_iref 0 HBLNA2_unit2_csbias_cs_iref_IDAC 0 HBLNA2_unit2_csbias_R 0 HBLNA2_unit2_csbias_vbias 0 HBLNA2_unit2_drainZ 0 HBLNA2_unit2_inputSH_ESD 0 HBLNA2_unit12_Ldeg 0 MBLNA1_unit1_csbias_cg_iref_IDAC 0 MBLNA1_unit1_csbias_cs_iref_IDAC 0 MBLNA1_unit2_csbias_cg_iref_IDAC 0 MBLNA1_unit2_csbias_cs_iref_IDAC 0 MBLNA1_unit3_csbias_cg_iref_IDAC 0 MBLNA1_unit3_csbias_cs_iref_IDAC 0 MBLNA2_unit1_csbias_cg_iref_IDAC 0 MBLNA2_unit1_csbias_cs_iref_IDAC 0 MBLNA2_unit2_csbias_cg_iref_IDAC 0 MBLNA2_unit2_csbias_cs_iref_IDAC 0 MBLNA2_unit3_csbias_cg_iref_IDAC 0 MBLNA2_unit3_csbias_cs_iref_IDAC 0 MBLNA3_unit1_csbias_cg_iref_IDAC 0 MBLNA3_unit1_csbias_cs_iref_IDAC 0 MBLNA3_unit2_csbias_cg_iref_IDAC 0 MBLNA3_unit2_csbias_cs_iref_IDAC 0 MBLNA3_unit3_csbias_cg_iref_IDAC 0 MBLNA3_unit3_csbias_cs_iref_IDAC 0 MLBLNA_unit1_csbias_cg_iref_IDAC 0 MLBLNA_unit1_csbias_cs_iref_IDAC 0 MLBLNA_unit2_csbias_cg_iref_IDAC 0 MLBLNA_unit2_csbias_cs_iref_IDAC 0 MUX_HB1_OUT1_se1 0 MUX_HB1_OUT1_se2 0 MUX_HB1_OUT1_sh 0 MUX_HB1_OUT2_se1 0 MUX_HB1_OUT2_se2 0 MUX_HB1_OUT2_sh 0 MUX_HB1_OUT3_se1 0 MUX_HB1_OUT3_se2 0 MUX_HB1_OUT3_sh 0 MUX_HB1_OUT4_se1 0 MUX_HB1_OUT4_se2 0 MUX_HB1_OUT4_sh 0 MUX_HB2_OUT1_se1 0 MUX_HB2_OUT1_se2 0 MUX_HB2_OUT1_sh 0 MUX_HB2_OUT2_se1 0 MUX_HB2_OUT2_se2 0 MUX_HB2_OUT2_sh 0 MUX_HB2_OUT3_se1 0 MUX_HB2_OUT3_se2 0 MUX_HB2_OUT3_sh 0 MUX_HB2_OUT4_se1 0 MUX_HB2_OUT4_se2 0 MUX_HB2_OUT4_sh 0 MUX_LMB_OUT1_se1 0 MUX_LMB_OUT1_se2 0 MUX_LMB_OUT1_sh 0 MUX_LMB_OUT2_se1 0 MUX_LMB_OUT2_se2 0 MUX_LMB_OUT2_sh 0 MUX_LMB_OUT3_se1 0 MUX_LMB_OUT3_se2 0 MUX_LMB_OUT3_sh 0 MUX_LMB_OUT4_se1 0 MUX_LMB_OUT4_se2 0 MUX_LMB_OUT4_sh 0 MUX_MB1_OUT1_se1 0 MUX_MB1_OUT1_se2 0 MUX_MB1_OUT1_sh 0 MUX_MB1_OUT2_se1 0 MUX_MB1_OUT2_se2 0 MUX_MB1_OUT2_sh 0 MUX_MB1_OUT3_se1 0 MUX_MB1_OUT3_se2 0 MUX_MB1_OUT3_sh 0 MUX_MB1_OUT4_se1 0 MUX_MB1_OUT4_se2 0 MUX_MB1_OUT4_sh 0 MUX_MB2_OUT1_se1 0 MUX_MB2_OUT1_se2 0 MUX_MB2_OUT1_sh 0 MUX_MB2_OUT2_se1 0 MUX_MB2_OUT2_se2 0 MUX_MB2_OUT2_sh 0 MUX_MB2_OUT3_se1 0 MUX_MB2_OUT3_se2 0 MUX_MB2_OUT3_sh 0 MUX_MB2_OUT4_se1 0 MUX_MB2_OUT4_se2 0 MUX_MB2_OUT4_sh 0 MUX_MB3_OUT1_se1 0 MUX_MB3_OUT1_se2 0 MUX_MB3_OUT1_sh 0 MUX_MB3_OUT2_se1 0 MUX_MB3_OUT2_se2 0 MUX_MB3_OUT2_sh 0 MUX_MB3_OUT3_se1 0 MUX_MB3_OUT3_se2 0 MUX_MB3_OUT3_sh 0 MUX_MB3_OUT4_se1 0 MUX_MB3_OUT4_se2 0 MUX_MB3_OUT4_sh 0 MUX_OUT1_Cs 0 MUX_OUT1_ESD 0 OUT4_MUX_0p5dBattn_res_in 0 OUT4_MUX_0p5dBattn_res_out 0 OUT4_MUX_0p5dBattn_se 0 OUT4_MUX_0p5dBattn_sh 0 OUT4_MUX_3dBattn_res_in 0 OUT4_MUX_3dBattn_res_out 0 OUT4_MUX_3dBattn_se 0 OUT4_MUX_3dBattn_sh 0 VDDDAC_cap 0 VDDDAC_HB1 0 VDDDAC_HB2 0 VDDDAC_MB1 0 VDDDAC_MB2 0 VDDDAC_MB3 0 VDDDAC_MLB 0 lam__001_LNA_U24_VDD 0 lam__087_LNA_U24_B1 0 lam__088_LNA_U24_B3 0 lam__089_LNA_U24_B4 0 lam__090_LNA_U24_B7 0 lam__091_LNA_U24_B25 0 lam__092_LNA_U24_B30 0 lam__093_LNA_U24_B34 0 lam__094_LNA_U24_B39 0 lam__095_LNA_U24_B40 0 lam__096_LNA_U24_B41 0 lam__097_LNA_U24_B70 0 lam__099_LNA_U24_B41H 0 lam__100_LNA_U24_B66R2 0 lam__102_LNA_U24_n75 0 ) nport file="/scratch/tfant/simulation/xxxxxx_tb/tb_em_fullchip_v3/maestro/results/maestro/Interactive.75/1/die01_hb2/netlist/v10_reduced_compressed_1.s194p" datafmt=touchstone,
while keeping the remaining instance parameter intact. In the current implementation, the voltages at the nodes that form the unused ports is set to zero. If you would like to turn this feature off, set the global option nportcompress to no.
**********************************************************************************************************************************
after having replaced the snp with a newly generated one and having edited some connections, the SP file is no longer compressed and the log file does not explain why. Is there a way to troubleshoot that ?
I tried several option (enable diagnostic, increase max warnings..) but it does not help. Also with the new Snp file most of the pots are unused, should it should be compressed.
thanks
Tommaso