Hi,
I have a fairly big mixed mode design, which has several configurations, (ie. different DC points, supplies, configurations etc). I've handled this with case-statements based on one variable, eg.:
variable conf = "A","B","X"
variable vdd = case(VAR("conf")("A" 1)("B" 2)("X" 3)(t 0))
etc.
Up until a recent update to the digital circuits this method has worked fine. Now, however it fails with the following:
ERROR (SFE-874): "path/to/input.scs" 8: 179: Unexpected open parenthesis "(". Expected close parenthesis or comma. Cannot run the simulation because of syntax error. Correct the error and rerun the simulation.
ERROR (SFE-683): "path/to/input.scs" 8: Badly formed parameters statement.
At line 179 in said input.scs, is just an ends to a subckt that holds some transistors, and not even any open parentheses.
Removing the case-statements solves the issue. However, I would really prefer to use the case statements, as they are very valuable in configuring my circuit for the roughly 360 configurations that I'm iterating through.
Any help is appreciated.
BR,
Christian
Versions information:
Virtuoso IC6.1.8-ISR14
Spectre 20.1
xrun 19.09
RH6