Plot voltage waveform at gate of transistor -RC extraction-.spf file

Hi, 

I am running post layout simulations in ADE Assembler. 

I want to plot the voltage waveform at the gate of a transistor in a RC extraction file (.spf) file. 

Do you know what is the correct format to include the net in the ADE Assembler output setup? 

In the .spf file this is the net I like to plot:

xbuf0/xinv2n<3>/xmn1/Mi0:GATE

This is a block at a lower hierarchy in my test-bench so in my "Output setup" I write: 

/cdr_vco/vco_biasvosc/osc/oschi/xbuf0/xinv2n<3>/xmn1/Mi0:GATE  

The RC extraction (.spf file) I have is for oschi  block.

but that doesn't seem to be working and I get error when trying to plot. 

Does anyone know what is the correct method/format to plot voltage at gate/drain of a transistor in RC extraction simulation?

Thanks a lot.

Best,

Hamed