Hi,
I am simulating a delay line made of 10 inverters (transient simulation with errpreset = conservative, and no transient noise).
The input clock to the delay line uses vpulse from analoglib with 100MHz frequency and 10p rise-time/fall-time.
I am measuring the delay (using calculator delay: rising to rising at Threshold = VDD/2) between the 2nd inverter and 4th inverter outputs and the delay between 4th inverter and 6th inverter outputs and I noticed the following:
1) The two delays are slightly different which should not be the case (2.248ps versus 2.25ps)
2) The results are again slightly different when I compare Spectre to APS
3) The clock at the output of the 2nd inverter for example has around 50fs jitter (when using APS) and this should not be the case.
What would be the best setting in order to get an accuracy within 10fs for example?
Thanks,
Imil