Hi,

I'm working with a circuit with more than one level of hierarchy like the following:

Each block has a resistor inside:

I made a layout for this that looks like the following (where I marked the terminals of the subcells):

As you can see, part of the routing is inside the subcells and the rest is outside. I made an extracted view of this layout using assura QRC and I created a netlist from this view. I found these parasitic resistors listed in the netlist:

    re2 (\1\:V1 \4\:V1) presistor r=316.615

    re3 (\4\:V1 V1) presistor r=10.4854

    re4 (\4\:V2 V2) presistor r=9.9263

    re5 (\2\:VNEG VNEG) presistor r=9.1725

    re6 (VSUB \1\:VSUB) presistor r=8.7516

    rd10 (\1\:V1 V1) presistor r=10.2233

    rd12 (\4\:V2 \5\:V2) presistor r=330.537

    rd11 (\5\:V2 V2) presistor r=10.1872

    rd7 (\2\:VREF VREF) presistor r=9.4185

I analyzed the netlist by hand and came to the conclusion that the circuit described has the following topology:

Question

My main goal was to probe the sub-blocks' terminals in a post-layout simulation (i.e. I want to know the voltages at the sub-blocks' pins taking into account all the parasitic resistors). I think I wouldn't be able to do this using the existing netlist since:

1) the nodes that correspond to the sub-blocks' pins don't appear in the netlist.

2) the topology is changed, the resistors stars are transformed to triangles.

Then my question is: How should I configure the extraction to preserve the circuit topology?

Additional info

Virtuoso version: IC6.1.8.500.08

Spectre version: SPECTRE 19.1.0.237.isr3

QRC version: EXT 18.2.1-s210

I think the issue may be related to the filtering options I used in the QRC form:

Thank you!