Hi,
I want to simulate a mixed signal design, with one cell on transistor-level and other cells as verilogams/vhdl models, with high accuracy (<2µV error).
One cell (called S2D) is modeled in verilogams, and is stimulated with an vsin source, and should convert the input stimulus to a wreal-value for further calculations in verilogams.
However, during simulation, I've noticed that the input is wrong, and the wreal-value does not match the analog value.
In the IE card setup, vdelta is set to 2u.
In the plot below, the interface element (input: analog voltage, output: wreal value) for the S2D input is shown.
In >90% of the transient simulation, the output (Dout, wreal) is equal with the Input (Ain, voltage) within the tolerance of +-2u.
However, there are some points where the difference is far too big, in the plot below for example 1,4mV!
Are there any other settings that affect the tolerances of the automatically inserted Interface elements?
Simulator is AMS, errorpreset conservative, Cadence Version IC6.1.8-64b.500.8.
