How can I monitor the terminal voltages all transistors in a transient simulation?

Hi,

I am performing transient simulations to a circuit in VIrtuoso ADE L with Cadence IC 6.1.7. I would like to monitor if the voltage difference across the terminals of any transistor in the whole circuit exceeds some value. Maybe by logging warning messages in which the time, device, and voltage value are identified. How can this be done?

Thanks in advanced.

Regards,

David.