VCO design problem

Hi all,

I am having a strange problem in designing my VCO.

The problem is: 

When I use this kind of biasing and sweep my ideal capacitor to change the frequency, freq varies but VCO output swing changes as well !!

The amplitude variation is low if I dont use that biasing and directing connect GateP to DrainN.

I dont understand what is the issue.

And also I dont want to want full swing for this VCO since if I have full swing the Vgd max will be high

I want to have swing of 1v pp so:

VD swing : (0.9 --> 1.9)

VG swing : (0.2 --> 1.2)

With this setup I prevent transistors entering triode region.

Thank you for your valuable time and effort.