Input Capacitance Measurements of Digital Cells in Cadence Liberate

Hi,

I have a requirement to characterize a set of standard cells of following type : 

All of these custom cells have the same transistor arrangement, i.e. a transmission gate pair followed by an inverter. Since the inverter isolates the inputs from the loads of the cell, this cell can be characterized over a wider slew/load range. A similar example can also be found in "Liberate - Characterization Setup for Special Mux Cells" RAK (i.e. MXIUI2X1) .

However the input capacitance values after the characterization seem to be quite larger than the values I observe in my spice simulation. 

Instead of manually updating the input capacitance in the .lib file using the spice data, is it possible to automatically calculate the correct values for these type of cells using Liberate itself ?

Thanks in advance

Anuradha