Regarding Simulation time in nc-verilog and in ADE-L/XL + AMS

Dear All,

I have a test-bench  (event based only) have the blocks written in verilog and VHDL.

I want to have the test-bench as schematic view. So I have drawn the test-bench in Schematic-Composer.

So, I can run it only through ADE-L + ams.

I want to know whether this way will have same simulation time as that of the run done by using nc-verilog commands in the terminal.

Can anybody please answer my query ?

Kind Regards,