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Cadence virtuoso version 6.2.145
I am using Cadence Virtuoso on RHEL 5.9 and I am trying to run a simple program but the image enclosed says some error. I have been trying to diagnose it for a while now but haven't got any success...
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design variables - parameters
Hi to everybody,I am using Cadence IC.6.1, and was trying to understand the difference in terms of utility between design variables and parameters (iPar, pPar). I already know that we set the design...
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gain
helloi am using virtuoso ic6.1.5. i want to find conversion gain of my circuit which have different input and output frequencies. which analysis should i use in cadence? why s parameter analysis donot...
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how to define a hot key to remove all probes in a schematic
Hi, All of you might use probes in schematic viewing. Along the way, you add more and more probes (by doing 9 and select nets). At some point you might want to remove all probes and start over by I...
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Hierarchy copy design questions (different view names)
Hi,I'd like to do the hierarchy copy to a self-contained library. How should I do? I'm okay to use SKILL or GUI operation. Thanks!The design has different libraries across the hierarchy which can be...
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load different display by a hot key
Hi All,There is a default display file from foundry and don't want to modify directly. But would like to use a different display file to load some personal settings. Can we define a short cut key to...
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[HELP] How to automatically place pins over a sub block on IC6.1.6 without...
Hi Cadence ForumI am working on a chip layout and I want to place the pins of the current hierarchy layout so that it will be over the pins of a sub block.Please see image below for clarity.Thank you...
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Dynamically Changing the pulse width - vpulse/vsource
I would like to generate variable pulse width based on the circuit conditions. I can use vpulse/vsource from analoglib to generate pulse with different duty cycles. But I am wondering, how to change or...
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turn off pulldown selection in ICADV12.3 ?
Hi, is there a way to turn off the pulldown selection in ICADV12.3, which appears in several places (library manager, and also in create new instance form), .e.g in the attached image, for create...
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Fail to run with user defined the "connect rules"
Hi EveryoneI want to introduce self-defined connectRules for AMS simulation to remove 1nsec sampling time from the predefined connectRules of the projectI have following the tutorial from Candence, and...
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How to set "case_sensitive=yes" with ocnDspfFile
ADE offers the inclusion of DSPF-files with the option that the internal nodes are interpreted case-sensitively.When doing the same with ocean via ocnDspfFile(...) , no option is offered to activated...
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Use via variant with auto via or via stack?
On the technology I am using the default via width for the top metal is not DRC clean for our application.I figured I could make a via variant to solve this.The issue is that once a variant is made,...
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Assura DRC doesn't zoom to errors
We are using Assura 4.15. When running DRC, the errors are listed in the ELW. When we try to locate the errors in the layout, error markers are visible (barely) because it does not "Zoom to Error"....
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Simulation of voltage doubler
I want to design a voltage doubler(Using Dickson charge pump with 2 clocks) withinput voltage=Vdd=3.3Voutput voltage=approximately =>6 voltsFrequency=1MHzcapacitance=5pFI took period of clock as 2...
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LAYOUT XL - auto route - route with wire assistant overrides
Hi ,Scenario : I am using cadence version IC6177 , layout xl and exploring auto route option for routing between analog modules. On right clicking the net , choosing the option .. net ->route with...
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VNCAP error
hi i am using virtuoso layout suite (v IC6.1.5.500.16.2). While using the vncap form technology library of 65nm CMOS; i am getting following error:" adjacent (interdigitated) Mx or By fingers must be...
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how to process parametric sweep result in adexl
hello, I have run 100 times tran sim by parametric sweep in adexl. In each run, I can use function "value" to find signal, Vx, at 5us. Then I can plot Vx by "plot all". Finally I can use function of...
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Simulation with verilog-a model
I am trying to simulate a memristor model and check basic operations.I got memristor source code written with verilog-a(below).module memristor (p, n) ;inout p, n ;electrical p, n ;parameter real uv =...
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Parameters Sweep in ADE-XL results in "netl err"
I'm trying to use ADE-XL to sweep "length" for a resistor pcell. I clicked "Parameters" in the "Data View" pane and I select a parameter to sweep in the schematic ADE-XL works correctly if:I don't set...
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How to tell spectre (in ADE L) to enable "monte carlo" mode
Hello,I am using an ST PDK ("ArtistKit") and I want to run a SIMPLE sim with local variations turned on. What I mean is that in a SINGLE RUN in ADE L, when I have two identical Common Source stages,...
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